)]}' { "commit": "5a9fb5a2bffe37bbfc525137946e6bc0809f6578", "tree": "49fb4e98c3ed00567fea35fd2869c94c8f2fc24e", "parents": [ "fc7cb70a7231bb7a92413d1f8b43c9f4ef6c8690" ], "author": { "name": "Gabor Dozsa", "email": "gabor.dozsa@arm.com", "time": "Thu Nov 15 17:21:57 2018 +0000" }, "committer": { "name": "Giacomo Gabrielli", "email": "giacomo.gabrielli@arm.com", "time": "Sun Jul 28 16:28:43 2019 +0000" }, "message": "cpu-o3: Fix too strict assert condition in writeback()\n\nThe assert() in the LSQ writeback() only allowed ReExec faults.\nHowever, a SplitRequest which completed the translation in\nPartialFault state (i.e. any but the very first cacheline\ntranslation failed) may end up here. The assert() condition is\nextended accordingly.\n\nThe patch also removes the superfluous/unused Complete/Squashed\nstates from the LSQ request. (The completion of the request is\nrecorded in the flags still.)\n\nChange-Id: Ie575f4d3b4d5295585828ad8c7d3f4c7c1fe15d0\nSigned-off-by: Gabor Dozsa \u003cgabor.dozsa@arm.com\u003e\nReviewed-by: Giacomo Gabrielli \u003cgiacomo.gabrielli@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19174\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Jason Lowe-Power \u003cjason@lowepower.com\u003e\nReviewed-by: Anthony Gutierrez \u003canthony.gutierrez@amd.com\u003e\nMaintainer: Jason Lowe-Power \u003cjason@lowepower.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "6f7820113f8a922f72e67aca34fedcbe00045efd", "old_mode": 33188, "old_path": "src/cpu/o3/lsq.hh", "new_id": "4701a8c9acc5a19d647b920390e3a3b34bb61011", "new_mode": 33188, "new_path": "src/cpu/o3/lsq.hh" }, { "type": "modify", "old_id": "27a563071e102b9ab750993de7eac0b63462b3a2", "old_mode": 33188, "old_path": "src/cpu/o3/lsq_impl.hh", "new_id": "a028424b0229f2897c7605c19ae0710e56114f5f", "new_mode": 33188, "new_path": "src/cpu/o3/lsq_impl.hh" }, { "type": "modify", "old_id": "b71ed7f78d2ef0cf8c1174cbed323d9d0a0018e0", "old_mode": 33188, "old_path": "src/cpu/o3/lsq_unit_impl.hh", "new_id": "c2483d56742892b1c5f6909520c9508ad337a3c3", "new_mode": 33188, "new_path": "src/cpu/o3/lsq_unit_impl.hh" } ] }