tree 632512ab699eee49207bedb2fb5ef19a57c9ddee
parent 2e47c6c5ed37dc1db0ea35f51b2f7d4afc0da45e
author Adrià Armejach <adria.armejach@gmail.com> 1534253239 +0200
committer Giacomo Gabrielli <giacomo.gabrielli@arm.com> 1564260691 +0000

arch-arm: Fix decoding for SVE memory instructions

Some SVE memory instructions are missing the makeSP function for
register operands that can be the SP register. This leads to
segmentation faults on the application side as the wrong register is
decoded.

Change-Id: Ic71abc845e0786a60d665231b5f7b024d2955f4b
Signed-off-by: Giacomo Gabrielli <giacomo.gabrielli@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/19169
Tested-by: kokoro <noreply+kokoro@google.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>