{
    "name": null, 
    "sim_quantum": 0, 
    "system": {
        "kernel": "", 
        "mmap_using_noreserve": false, 
        "kernel_addr_check": true, 
        "rom": {
            "range": "1099243192320:1099251580927:0:0:0:0", 
            "latency": 60, 
            "name": "rom", 
            "p_state_clk_gate_min": 2, 
            "eventq_index": 0, 
            "p_state_clk_gate_bins": 20, 
            "default_p_state": "UNDEFINED", 
            "kvm_map": true, 
            "clk_domain": "system.clk_domain", 
            "power_model": null, 
            "latency_var": 0, 
            "bandwidth": "0.000000", 
            "conf_table_reported": true, 
            "cxx_class": "SimpleMemory", 
            "p_state_clk_gate_max": 2000000000, 
            "path": "system.rom", 
            "null": false, 
            "type": "SimpleMemory", 
            "port": {
                "peer": "system.membus.master[3]", 
                "role": "SLAVE"
            }, 
            "in_addr_map": true
        }, 
        "bridge": {
            "ranges": [
                "133412421632:133412421639:0:0:0:0", 
                "134217728000:554050781183:0:0:0:0", 
                "644245094400:652835028991:0:0:0:0", 
                "725849473024:1095485095935:0:0:0:0", 
                "1099255955456:1099255955463:0:0:0:0"
            ], 
            "slave": {
                "peer": "system.membus.master[2]", 
                "role": "SLAVE"
            }, 
            "name": "bridge", 
            "p_state_clk_gate_min": 2, 
            "p_state_clk_gate_bins": 20, 
            "cxx_class": "Bridge", 
            "req_size": 16, 
            "clk_domain": "system.clk_domain", 
            "power_model": null, 
            "delay": 100, 
            "eventq_index": 0, 
            "master": {
                "peer": "system.iobus.slave[0]", 
                "role": "MASTER"
            }, 
            "default_p_state": "UNDEFINED", 
            "p_state_clk_gate_max": 2000000000, 
            "path": "system.bridge", 
            "resp_size": 16, 
            "type": "Bridge"
        }, 
        "iobus": {
            "forward_latency": 1, 
            "slave": {
                "peer": [
                    "system.bridge.master"
                ], 
                "role": "SLAVE"
            }, 
            "name": "iobus", 
            "p_state_clk_gate_min": 2, 
            "p_state_clk_gate_bins": 20, 
            "cxx_class": "NoncoherentXBar", 
            "clk_domain": "system.clk_domain", 
            "power_model": null, 
            "width": 16, 
            "eventq_index": 0, 
            "master": {
                "peer": [
                    "system.t1000.fake_clk.pio", 
                    "system.t1000.fake_membnks.pio", 
                    "system.t1000.fake_l2_1.pio", 
                    "system.t1000.fake_l2_2.pio", 
                    "system.t1000.fake_l2_3.pio", 
                    "system.t1000.fake_l2_4.pio", 
                    "system.t1000.fake_l2esr_1.pio", 
                    "system.t1000.fake_l2esr_2.pio", 
                    "system.t1000.fake_l2esr_3.pio", 
                    "system.t1000.fake_l2esr_4.pio", 
                    "system.t1000.fake_ssi.pio", 
                    "system.t1000.fake_jbi.pio", 
                    "system.t1000.puart0.pio", 
                    "system.t1000.hvuart.pio", 
                    "system.disk0.pio"
                ], 
                "role": "MASTER"
            }, 
            "response_latency": 2, 
            "default_p_state": "UNDEFINED", 
            "p_state_clk_gate_max": 2000000000, 
            "path": "system.iobus", 
            "type": "NoncoherentXBar", 
            "use_default_range": false, 
            "frontend_latency": 2
        }, 
        "t1000": {
            "htod": {
                "name": "htod", 
                "p_state_clk_gate_min": 2, 
                "pio": {
                    "peer": "system.membus.master[1]", 
                    "role": "SLAVE"
                }, 
                "p_state_clk_gate_bins": 20, 
                "cxx_class": "DumbTOD", 
                "pio_latency": 200, 
                "clk_domain": "system.clk_domain", 
                "power_model": null, 
                "system": "system", 
                "eventq_index": 0, 
                "time": "Thu Jan  1 00:00:00 2009", 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "path": "system.t1000.htod", 
                "pio_addr": 1099255906296, 
                "type": "DumbTOD"
            }, 
            "puart0": {
                "name": "puart0", 
                "p_state_clk_gate_min": 2, 
                "pio": {
                    "peer": "system.iobus.master[12]", 
                    "role": "SLAVE"
                }, 
                "p_state_clk_gate_bins": 20, 
                "cxx_class": "Uart8250", 
                "pio_latency": 200, 
                "clk_domain": "system.clk_domain", 
                "power_model": null, 
                "system": "system", 
                "terminal": "system.t1000.pterm", 
                "platform": "system.t1000", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "path": "system.t1000.puart0", 
                "pio_addr": 133412421632, 
                "type": "Uart8250"
            }, 
            "fake_membnks": {
                "pio": {
                    "peer": "system.iobus.master[1]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 0, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 648540061696, 
                "update_data": false, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_membnks", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_membnks", 
                "ret_bad_addr": false, 
                "pio_size": 16384, 
                "p_state_clk_gate_bins": 20
            }, 
            "cxx_class": "T1000", 
            "fake_jbi": {
                "pio": {
                    "peer": "system.iobus.master[11]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 18446744073709551615, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 549755813888, 
                "update_data": false, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_jbi", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_jbi", 
                "ret_bad_addr": false, 
                "pio_size": 4294967296, 
                "p_state_clk_gate_bins": 20
            }, 
            "intrctrl": "system.intrctrl", 
            "fake_l2esr_2": {
                "pio": {
                    "peer": "system.iobus.master[7]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 0, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 734439407680, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2esr_2", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2esr_2", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "system": "system", 
            "eventq_index": 0, 
            "hterm": {
                "name": "hterm", 
                "output": true, 
                "number": 0, 
                "intr_control": "system.intrctrl", 
                "eventq_index": 0, 
                "cxx_class": "Terminal", 
                "path": "system.t1000.hterm", 
                "type": "Terminal", 
                "port": 3456
            }, 
            "type": "T1000", 
            "fake_l2_4": {
                "pio": {
                    "peer": "system.iobus.master[5]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 1, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 725849473216, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2_4", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2_4", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "fake_l2_1": {
                "pio": {
                    "peer": "system.iobus.master[2]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 1, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 725849473024, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2_1", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2_1", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "fake_l2_2": {
                "pio": {
                    "peer": "system.iobus.master[3]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 1, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 725849473088, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2_2", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2_2", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "fake_l2_3": {
                "pio": {
                    "peer": "system.iobus.master[4]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 1, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 725849473152, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2_3", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2_3", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "pterm": {
                "name": "pterm", 
                "output": true, 
                "number": 0, 
                "intr_control": "system.intrctrl", 
                "eventq_index": 0, 
                "cxx_class": "Terminal", 
                "path": "system.t1000.pterm", 
                "type": "Terminal", 
                "port": 3456
            }, 
            "path": "system.t1000", 
            "iob": {
                "name": "iob", 
                "p_state_clk_gate_min": 2, 
                "pio": {
                    "peer": "system.membus.master[0]", 
                    "role": "SLAVE"
                }, 
                "p_state_clk_gate_bins": 20, 
                "cxx_class": "Iob", 
                "pio_latency": 2, 
                "clk_domain": "system.clk_domain", 
                "power_model": null, 
                "system": "system", 
                "platform": "system.t1000", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "path": "system.t1000.iob", 
                "type": "Iob"
            }, 
            "hvuart": {
                "name": "hvuart", 
                "p_state_clk_gate_min": 2, 
                "pio": {
                    "peer": "system.iobus.master[13]", 
                    "role": "SLAVE"
                }, 
                "p_state_clk_gate_bins": 20, 
                "cxx_class": "Uart8250", 
                "pio_latency": 200, 
                "clk_domain": "system.clk_domain", 
                "power_model": null, 
                "system": "system", 
                "terminal": "system.t1000.hterm", 
                "platform": "system.t1000", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "path": "system.t1000.hvuart", 
                "pio_addr": 1099255955456, 
                "type": "Uart8250"
            }, 
            "name": "t1000", 
            "fake_l2esr_3": {
                "pio": {
                    "peer": "system.iobus.master[8]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 0, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 734439407744, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2esr_3", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2esr_3", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "fake_ssi": {
                "pio": {
                    "peer": "system.iobus.master[10]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 18446744073709551615, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 1095216660480, 
                "update_data": false, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_ssi", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_ssi", 
                "ret_bad_addr": false, 
                "pio_size": 268435456, 
                "p_state_clk_gate_bins": 20
            }, 
            "fake_l2esr_1": {
                "pio": {
                    "peer": "system.iobus.master[6]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 0, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 734439407616, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2esr_1", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2esr_1", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "fake_l2esr_4": {
                "pio": {
                    "peer": "system.iobus.master[9]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 0, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 734439407808, 
                "update_data": true, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_l2esr_4", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_l2esr_4", 
                "ret_bad_addr": false, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "fake_clk": {
                "pio": {
                    "peer": "system.iobus.master[0]", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 18446744073709551615, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 644245094400, 
                "update_data": false, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.t1000.fake_clk", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "fake_clk", 
                "ret_bad_addr": false, 
                "pio_size": 4294967296, 
                "p_state_clk_gate_bins": 20
            }
        }, 
        "partition_desc_addr": 133445976064, 
        "symbolfile": "", 
        "readfile": "/usr/local/google/home/gabeblack/gem5/gem5-public/tests/testing/../halt.sh", 
        "thermal_model": null, 
        "hypervisor_addr": 1099243257856, 
        "mem_ranges": [
            "1048576:68157439:0:0:0:0", 
            "2147483648:2415919103:0:0:0:0"
        ], 
        "cxx_class": "SparcSystem", 
        "work_begin_cpu_id_exit": -1, 
        "load_offset": 0, 
        "reset_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/reset_new.bin", 
        "work_end_ckpt_count": 0, 
        "work_begin_exit_count": 0, 
        "openboot_addr": 1099243716608, 
        "p_state_clk_gate_min": 2, 
        "nvram_addr": 133429198848, 
        "memories": [
            "system.hypervisor_desc", 
            "system.nvram", 
            "system.partition_desc", 
            "system.physmem0", 
            "system.physmem1", 
            "system.rom"
        ], 
        "work_begin_ckpt_count": 0, 
        "partition_desc": {
            "range": "133445976064:133445984255:0:0:0:0", 
            "latency": 60, 
            "name": "partition_desc", 
            "p_state_clk_gate_min": 2, 
            "eventq_index": 0, 
            "p_state_clk_gate_bins": 20, 
            "default_p_state": "UNDEFINED", 
            "kvm_map": true, 
            "clk_domain": "system.clk_domain", 
            "power_model": null, 
            "latency_var": 0, 
            "bandwidth": "0.000000", 
            "conf_table_reported": true, 
            "cxx_class": "SimpleMemory", 
            "p_state_clk_gate_max": 2000000000, 
            "path": "system.partition_desc", 
            "null": false, 
            "type": "SimpleMemory", 
            "port": {
                "peer": "system.membus.master[6]", 
                "role": "SLAVE"
            }, 
            "in_addr_map": true
        }, 
        "clk_domain": {
            "name": "clk_domain", 
            "clock": [
                2
            ], 
            "init_perf_level": 0, 
            "voltage_domain": "system.voltage_domain", 
            "eventq_index": 0, 
            "cxx_class": "SrcClockDomain", 
            "path": "system.clk_domain", 
            "type": "SrcClockDomain", 
            "domain_id": -1
        }, 
        "hypervisor_desc": {
            "range": "133446500352:133446508543:0:0:0:0", 
            "latency": 60, 
            "name": "hypervisor_desc", 
            "p_state_clk_gate_min": 2, 
            "eventq_index": 0, 
            "p_state_clk_gate_bins": 20, 
            "default_p_state": "UNDEFINED", 
            "kvm_map": true, 
            "clk_domain": "system.clk_domain", 
            "power_model": null, 
            "latency_var": 0, 
            "bandwidth": "0.000000", 
            "conf_table_reported": true, 
            "cxx_class": "SimpleMemory", 
            "p_state_clk_gate_max": 2000000000, 
            "path": "system.hypervisor_desc", 
            "null": false, 
            "type": "SimpleMemory", 
            "port": {
                "peer": "system.membus.master[5]", 
                "role": "SLAVE"
            }, 
            "in_addr_map": true
        }, 
        "membus": {
            "point_of_coherency": true, 
            "system": "system", 
            "response_latency": 2, 
            "cxx_class": "CoherentXBar", 
            "badaddr_responder": {
                "pio": {
                    "peer": "system.membus.default", 
                    "role": "SLAVE"
                }, 
                "ret_data64": 18446744073709551615, 
                "fake_mem": false, 
                "clk_domain": "system.clk_domain", 
                "cxx_class": "IsaFake", 
                "pio_addr": 0, 
                "update_data": false, 
                "warn_access": "", 
                "pio_latency": 200, 
                "system": "system", 
                "eventq_index": 0, 
                "default_p_state": "UNDEFINED", 
                "p_state_clk_gate_max": 2000000000, 
                "type": "IsaFake", 
                "p_state_clk_gate_min": 2, 
                "power_model": null, 
                "ret_data32": 4294967295, 
                "path": "system.membus.badaddr_responder", 
                "ret_data16": 65535, 
                "ret_data8": 255, 
                "name": "badaddr_responder", 
                "ret_bad_addr": true, 
                "pio_size": 8, 
                "p_state_clk_gate_bins": 20
            }, 
            "forward_latency": 4, 
            "clk_domain": "system.clk_domain", 
            "width": 16, 
            "eventq_index": 0, 
            "default_p_state": "UNDEFINED", 
            "p_state_clk_gate_max": 2000000000, 
            "master": {
                "peer": [
                    "system.t1000.iob.pio", 
                    "system.t1000.htod.pio", 
                    "system.bridge.slave", 
                    "system.rom.port", 
                    "system.nvram.port", 
                    "system.hypervisor_desc.port", 
                    "system.partition_desc.port", 
                    "system.physmem0.port", 
                    "system.physmem1.port"
                ], 
                "role": "MASTER"
            }, 
            "type": "CoherentXBar", 
            "frontend_latency": 3, 
            "slave": {
                "peer": [
                    "system.system_port", 
                    "system.cpu.icache_port", 
                    "system.cpu.dcache_port"
                ], 
                "role": "SLAVE"
            }, 
            "p_state_clk_gate_min": 2, 
            "snoop_filter": {
                "name": "snoop_filter", 
                "system": "system", 
                "max_capacity": 8388608, 
                "eventq_index": 0, 
                "cxx_class": "SnoopFilter", 
                "path": "system.membus.snoop_filter", 
                "type": "SnoopFilter", 
                "lookup_latency": 1
            }, 
            "power_model": null, 
            "path": "system.membus", 
            "snoop_response_latency": 4, 
            "name": "membus", 
            "default": {
                "peer": "system.membus.badaddr_responder.pio", 
                "role": "MASTER"
            }, 
            "p_state_clk_gate_bins": 20, 
            "use_default_range": false
        }, 
        "nvram": {
            "range": "133429198848:133429207039:0:0:0:0", 
            "latency": 60, 
            "name": "nvram", 
            "p_state_clk_gate_min": 2, 
            "eventq_index": 0, 
            "p_state_clk_gate_bins": 20, 
            "default_p_state": "UNDEFINED", 
            "kvm_map": true, 
            "clk_domain": "system.clk_domain", 
            "power_model": null, 
            "latency_var": 0, 
            "bandwidth": "0.000000", 
            "conf_table_reported": true, 
            "cxx_class": "SimpleMemory", 
            "p_state_clk_gate_max": 2000000000, 
            "path": "system.nvram", 
            "null": false, 
            "type": "SimpleMemory", 
            "port": {
                "peer": "system.membus.master[4]", 
                "role": "SLAVE"
            }, 
            "in_addr_map": true
        }, 
        "eventq_index": 0, 
        "default_p_state": "UNDEFINED", 
        "p_state_clk_gate_max": 2000000000, 
        "dvfs_handler": {
            "enable": false, 
            "name": "dvfs_handler", 
            "sys_clk_domain": "system.clk_domain", 
            "transition_latency": 200000, 
            "eventq_index": 0, 
            "cxx_class": "DVFSHandler", 
            "domains": [], 
            "path": "system.dvfs_handler", 
            "type": "DVFSHandler"
        }, 
        "work_end_exit_count": 0, 
        "hypervisor_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-hv.bin", 
        "openboot_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/openboot_new.bin", 
        "voltage_domain": {
            "name": "voltage_domain", 
            "eventq_index": 0, 
            "voltage": [
                "1.0"
            ], 
            "cxx_class": "VoltageDomain", 
            "path": "system.voltage_domain", 
            "type": "VoltageDomain"
        }, 
        "cache_line_size": 64, 
        "boot_osflags": "a", 
        "system_port": {
            "peer": "system.membus.slave[0]", 
            "role": "MASTER"
        }, 
        "physmem": [
            {
                "range": "1048576:68157439:0:0:0:0", 
                "latency": 60, 
                "name": "physmem0", 
                "p_state_clk_gate_min": 2, 
                "eventq_index": 0, 
                "p_state_clk_gate_bins": 20, 
                "default_p_state": "UNDEFINED", 
                "kvm_map": true, 
                "clk_domain": "system.clk_domain", 
                "power_model": null, 
                "latency_var": 0, 
                "bandwidth": "0.000000", 
                "conf_table_reported": true, 
                "cxx_class": "SimpleMemory", 
                "p_state_clk_gate_max": 2000000000, 
                "path": "system.physmem0", 
                "null": false, 
                "type": "SimpleMemory", 
                "port": {
                    "peer": "system.membus.master[7]", 
                    "role": "SLAVE"
                }, 
                "in_addr_map": true
            }, 
            {
                "range": "2147483648:2415919103:0:0:0:0", 
                "latency": 60, 
                "name": "physmem1", 
                "p_state_clk_gate_min": 2, 
                "eventq_index": 0, 
                "p_state_clk_gate_bins": 20, 
                "default_p_state": "UNDEFINED", 
                "kvm_map": true, 
                "clk_domain": "system.clk_domain", 
                "power_model": null, 
                "latency_var": 0, 
                "bandwidth": "0.000000", 
                "conf_table_reported": true, 
                "cxx_class": "SimpleMemory", 
                "p_state_clk_gate_max": 2000000000, 
                "path": "system.physmem1", 
                "null": false, 
                "type": "SimpleMemory", 
                "port": {
                    "peer": "system.membus.master[8]", 
                    "role": "SLAVE"
                }, 
                "in_addr_map": true
            }
        ], 
        "power_model": null, 
        "work_cpus_ckpt_count": 0, 
        "thermal_components": [], 
        "path": "system", 
        "hypervisor_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/q_new.bin", 
        "cpu_clk_domain": {
            "name": "cpu_clk_domain", 
            "clock": [
                2
            ], 
            "init_perf_level": 0, 
            "voltage_domain": "system.voltage_domain", 
            "eventq_index": 0, 
            "cxx_class": "SrcClockDomain", 
            "path": "system.cpu_clk_domain", 
            "type": "SrcClockDomain", 
            "domain_id": -1
        }, 
        "nvram_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/nvram1", 
        "mem_mode": "atomic", 
        "name": "system", 
        "init_param": 0, 
        "type": "SparcSystem", 
        "partition_desc_bin": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/binaries/1up-md.bin", 
        "load_addr_mask": 1099511627775, 
        "cpu": {
            "do_statistics_insts": true, 
            "numThreads": 1, 
            "itb": {
                "name": "itb", 
                "eventq_index": 0, 
                "cxx_class": "SparcISA::TLB", 
                "path": "system.cpu.itb", 
                "type": "SparcTLB", 
                "size": 64
            }, 
            "simulate_data_stalls": false, 
            "function_trace": false, 
            "do_checkpoint_insts": true, 
            "cxx_class": "AtomicSimpleCPU", 
            "max_loads_all_threads": 0, 
            "system": "system", 
            "clk_domain": "system.cpu_clk_domain", 
            "function_trace_start": 0, 
            "cpu_id": 0, 
            "width": 1, 
            "checker": null, 
            "eventq_index": 0, 
            "default_p_state": "UNDEFINED", 
            "p_state_clk_gate_max": 2000000000, 
            "do_quiesce": true, 
            "type": "AtomicSimpleCPU", 
            "fastmem": false, 
            "profile": 0, 
            "icache_port": {
                "peer": "system.membus.slave[1]", 
                "role": "MASTER"
            }, 
            "p_state_clk_gate_bins": 20, 
            "p_state_clk_gate_min": 2, 
            "interrupts": [
                {
                    "eventq_index": 0, 
                    "path": "system.cpu.interrupts", 
                    "type": "SparcInterrupts", 
                    "name": "interrupts", 
                    "cxx_class": "SparcISA::Interrupts"
                }
            ], 
            "dcache_port": {
                "peer": "system.membus.slave[2]", 
                "role": "MASTER"
            }, 
            "socket_id": 0, 
            "power_model": null, 
            "max_insts_all_threads": 0, 
            "path": "system.cpu", 
            "max_loads_any_thread": 0, 
            "switched_out": false, 
            "workload": [], 
            "name": "cpu", 
            "dtb": {
                "name": "dtb", 
                "eventq_index": 0, 
                "cxx_class": "SparcISA::TLB", 
                "path": "system.cpu.dtb", 
                "type": "SparcTLB", 
                "size": 64
            }, 
            "simpoint_start_insts": [], 
            "max_insts_any_thread": 0, 
            "simulate_inst_stalls": false, 
            "progress_interval": 0, 
            "branchPred": null, 
            "isa": [
                {
                    "eventq_index": 0, 
                    "path": "system.cpu.isa", 
                    "type": "SparcISA", 
                    "name": "isa", 
                    "cxx_class": "SparcISA::ISA"
                }
            ], 
            "tracer": {
                "eventq_index": 0, 
                "path": "system.cpu.tracer", 
                "type": "ExeTracer", 
                "name": "tracer", 
                "cxx_class": "Trace::ExeTracer"
            }
        }, 
        "intrctrl": {
            "name": "intrctrl", 
            "sys": "system", 
            "eventq_index": 0, 
            "cxx_class": "IntrControl", 
            "path": "system.intrctrl", 
            "type": "IntrControl"
        }, 
        "disk0": {
            "name": "disk0", 
            "p_state_clk_gate_min": 2, 
            "pio": {
                "peer": "system.iobus.master[14]", 
                "role": "SLAVE"
            }, 
            "p_state_clk_gate_bins": 20, 
            "image": {
                "read_only": false, 
                "name": "image", 
                "cxx_class": "CowDiskImage", 
                "eventq_index": 0, 
                "child": {
                    "read_only": true, 
                    "name": "child", 
                    "eventq_index": 0, 
                    "cxx_class": "RawDiskImage", 
                    "path": "system.disk0.image.child", 
                    "image_file": "/usr/local/google/home/gabeblack/gem5/dist/m5/system/disks/disk.s10hw2", 
                    "type": "RawDiskImage"
                }, 
                "path": "system.disk0.image", 
                "image_file": "", 
                "type": "CowDiskImage", 
                "table_size": 65536
            }, 
            "cxx_class": "MmDisk", 
            "pio_latency": 200, 
            "clk_domain": "system.clk_domain", 
            "power_model": null, 
            "system": "system", 
            "eventq_index": 0, 
            "default_p_state": "UNDEFINED", 
            "p_state_clk_gate_max": 2000000000, 
            "path": "system.disk0", 
            "pio_addr": 134217728000, 
            "type": "MmDisk"
        }, 
        "multi_thread": false, 
        "reset_addr": 1099243192320, 
        "p_state_clk_gate_bins": 20, 
        "hypervisor_desc_addr": 133446500352, 
        "num_work_ids": 16, 
        "work_item_id": -1, 
        "exit_on_work_items": false
    }, 
    "time_sync_period": 200000000, 
    "eventq_index": 0, 
    "time_sync_spin_threshold": 200000, 
    "cxx_class": "Root", 
    "path": "root", 
    "time_sync_enable": false, 
    "type": "Root", 
    "full_system": true
}