/*
 * Copyright (c) 2010-2012, 2016-2017, 2019 ARM Limited
 * Copyright (c) 2013 Advanced Micro Devices, Inc.
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 * to a hardware implementation of the functionality of the software
 * licensed hereunder.  You may use the software subject to the license
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 * modified or unmodified, in source code or in binary form.
 *
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 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * neither the name of the copyright holders nor the names of its
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#ifndef __CPU_O3_THREAD_CONTEXT_IMPL_HH__
#define __CPU_O3_THREAD_CONTEXT_IMPL_HH__

#include "arch/generic/traits.hh"
#include "arch/registers.hh"
#include "config/the_isa.hh"
#include "cpu/o3/thread_context.hh"
#include "debug/O3CPU.hh"

template <class Impl>
PortProxy&
O3ThreadContext<Impl>::getVirtProxy()
{
    return thread->getVirtProxy();
}

template <class Impl>
void
O3ThreadContext<Impl>::takeOverFrom(ThreadContext *old_context)
{
    ::takeOverFrom(*this, *old_context);

    this->getIsaPtr()->takeOverFrom(this, old_context);

    TheISA::Decoder *newDecoder = getDecoderPtr();
    TheISA::Decoder *oldDecoder = old_context->getDecoderPtr();
    newDecoder->takeOverFrom(oldDecoder);

    thread->funcExeInst = old_context->readFuncExeInst();

    thread->noSquashFromTC = false;
    thread->trapPending = false;
}

template <class Impl>
void
O3ThreadContext<Impl>::activate()
{
    DPRINTF(O3CPU, "Calling activate on Thread Context %d\n",
            threadId());

    if (thread->status() == ThreadContext::Active)
        return;

    thread->lastActivate = curTick();
    thread->setStatus(ThreadContext::Active);

    // status() == Suspended
    cpu->activateContext(thread->threadId());
}

template <class Impl>
void
O3ThreadContext<Impl>::suspend()
{
    DPRINTF(O3CPU, "Calling suspend on Thread Context %d\n",
            threadId());

    if (thread->status() == ThreadContext::Suspended)
        return;

    if (cpu->isDraining()) {
        DPRINTF(O3CPU, "Ignoring suspend on TC due to pending drain\n");
        return;
    }

    thread->lastActivate = curTick();
    thread->lastSuspend = curTick();

    thread->setStatus(ThreadContext::Suspended);
    cpu->suspendContext(thread->threadId());
}

template <class Impl>
void
O3ThreadContext<Impl>::halt()
{
    DPRINTF(O3CPU, "Calling halt on Thread Context %d\n", threadId());

    if (thread->status() == ThreadContext::Halting ||
        thread->status() == ThreadContext::Halted)
        return;

    // the thread is not going to halt/terminate immediately in this cycle.
    // The thread will be removed after an exit trap is processed
    // (e.g., after trapLatency cycles). Until then, the thread's status
    // will be Halting.
    thread->setStatus(ThreadContext::Halting);

    // add this thread to the exiting list to mark that it is trying to exit.
    cpu->addThreadToExitingList(thread->threadId());
}

template <class Impl>
Tick
O3ThreadContext<Impl>::readLastActivate()
{
    return thread->lastActivate;
}

template <class Impl>
Tick
O3ThreadContext<Impl>::readLastSuspend()
{
    return thread->lastSuspend;
}

template <class Impl>
void
O3ThreadContext<Impl>::copyArchRegs(ThreadContext *tc)
{
    // Set vector renaming mode before copying registers
    cpu->vecRenameMode(RenameMode<TheISA::ISA>::mode(tc->pcState()));

    // Prevent squashing
    thread->noSquashFromTC = true;
    TheISA::copyRegs(tc, this);
    thread->noSquashFromTC = false;

    if (!FullSystem)
        this->thread->funcExeInst = tc->readFuncExeInst();
}

template <class Impl>
void
O3ThreadContext<Impl>::clearArchRegs()
{
    cpu->isa[thread->threadId()]->clear();
}

template <class Impl>
RegVal
O3ThreadContext<Impl>::readIntRegFlat(RegIndex reg_idx) const
{
    return cpu->readArchIntReg(reg_idx, thread->threadId());
}

template <class Impl>
RegVal
O3ThreadContext<Impl>::readFloatRegFlat(RegIndex reg_idx) const
{
    return cpu->readArchFloatReg(reg_idx, thread->threadId());
}

template <class Impl>
const TheISA::VecRegContainer&
O3ThreadContext<Impl>::readVecRegFlat(RegIndex reg_id) const
{
    return cpu->readArchVecReg(reg_id, thread->threadId());
}

template <class Impl>
TheISA::VecRegContainer&
O3ThreadContext<Impl>::getWritableVecRegFlat(RegIndex reg_id)
{
    return cpu->getWritableArchVecReg(reg_id, thread->threadId());
}

template <class Impl>
const TheISA::VecElem&
O3ThreadContext<Impl>::readVecElemFlat(RegIndex idx,
                                       const ElemIndex& elemIndex) const
{
    return cpu->readArchVecElem(idx, elemIndex, thread->threadId());
}

template <class Impl>
const TheISA::VecPredRegContainer&
O3ThreadContext<Impl>::readVecPredRegFlat(RegIndex reg_id) const
{
    return cpu->readArchVecPredReg(reg_id, thread->threadId());
}

template <class Impl>
TheISA::VecPredRegContainer&
O3ThreadContext<Impl>::getWritableVecPredRegFlat(RegIndex reg_id)
{
    return cpu->getWritableArchVecPredReg(reg_id, thread->threadId());
}

template <class Impl>
RegVal
O3ThreadContext<Impl>::readCCRegFlat(RegIndex reg_idx) const
{
    return cpu->readArchCCReg(reg_idx, thread->threadId());
}

template <class Impl>
void
O3ThreadContext<Impl>::setIntRegFlat(RegIndex reg_idx, RegVal val)
{
    cpu->setArchIntReg(reg_idx, val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::setFloatRegFlat(RegIndex reg_idx, RegVal val)
{
    cpu->setArchFloatReg(reg_idx, val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::setVecRegFlat(
        RegIndex reg_idx, const VecRegContainer& val)
{
    cpu->setArchVecReg(reg_idx, val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::setVecElemFlat(RegIndex idx,
        const ElemIndex& elemIndex, const VecElem& val)
{
    cpu->setArchVecElem(idx, elemIndex, val, thread->threadId());
    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::setVecPredRegFlat(RegIndex reg_idx,
                                         const VecPredRegContainer& val)
{
    cpu->setArchVecPredReg(reg_idx, val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::setCCRegFlat(RegIndex reg_idx, RegVal val)
{
    cpu->setArchCCReg(reg_idx, val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::pcState(const TheISA::PCState &val)
{
    cpu->pcState(val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::pcStateNoRecord(const TheISA::PCState &val)
{
    cpu->pcState(val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
RegId
O3ThreadContext<Impl>::flattenRegId(const RegId& regId) const
{
    return cpu->isa[thread->threadId()]->flattenRegId(regId);
}

template <class Impl>
void
O3ThreadContext<Impl>::setMiscRegNoEffect(RegIndex misc_reg, RegVal val)
{
    cpu->setMiscRegNoEffect(misc_reg, val, thread->threadId());

    conditionalSquash();
}

template <class Impl>
void
O3ThreadContext<Impl>::setMiscReg(RegIndex misc_reg, RegVal val)
{
    cpu->setMiscReg(misc_reg, val, thread->threadId());

    conditionalSquash();
}

// hardware transactional memory
template <class Impl>
void
O3ThreadContext<Impl>::htmAbortTransaction(uint64_t htmUid,
                                           HtmFailureFaultCause cause)
{
    cpu->htmSendAbortSignal(thread->threadId(), htmUid, cause);

    conditionalSquash();
}

template <class Impl>
BaseHTMCheckpointPtr&
O3ThreadContext<Impl>::getHtmCheckpointPtr()
{
    return thread->htmCheckpoint;
}

template <class Impl>
void
O3ThreadContext<Impl>::setHtmCheckpointPtr(BaseHTMCheckpointPtr new_cpt)
{
    thread->htmCheckpoint = std::move(new_cpt);
}

#endif //__CPU_O3_THREAD_CONTEXT_IMPL_HH__