tree 94c1ba9269e3a6ebd856198e816da8dcd58e09d2
parent dd2f1fb2f8520849f10fc25fc5eab5beaa90a7d4
author Hoa Nguyen <hoanguyen@ucdavis.edu> 1667518973 -0700
committer Hoa Nguyen <hoanguyen@ucdavis.edu> 1667695510 +0000

arch-riscv: Updating the SD bit of mstatus upon the register read

Per RISC-V ISA Manual, vol II, section 3.1.6.6, page 26, the SD bit is
a read-only bit indicating whether any of FS, VS, and XS fields being
in the respective dirty state.

Per section 3.1.6, page 20, the SD bit is the most significant bit of
the mstatus register for both RV32 and RV64.

Per section 3.1.6.6, page 29, the explicit formula for updating the SD is,
    SD = ((FS==DIRTY) | (XS==DIRTY) | (VS==DIRTY))

Previously in gem5, this bit is not updated anywhere in the gem5
implementation. This cause an issue of incorrectly saving the context
before entering the system call and consequently, incorecttly restoring
the context after a system call as described here [1].

Ideally, we want to update the SD after every relevant instruction;
however, lazily updating the Status register upon its read produces
the same effect.

[1] https://gem5-review.googlesource.com/c/public/gem5/+/65272/

Change-Id: I1db0cc619d43bc5bacb1d03f6f214345d9d90e28
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65273
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>