arch-arm: Rework the int regs.
Change-Id: I352e12d4742f0771859bdbf9634ac87e2c153427
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49764
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
diff --git a/src/arch/arm/aapcs32.hh b/src/arch/arm/aapcs32.hh
index 5cb1c8e..88406e9 100644
--- a/src/arch/arm/aapcs32.hh
+++ b/src/arch/arm/aapcs32.hh
@@ -64,7 +64,7 @@
Addr retAddr=0;
explicit State(const ThreadContext *tc) :
- nsaa(tc->readIntReg(ArmISA::INTREG_SPX))
+ nsaa(tc->getReg(ArmISA::int_reg::Spx))
{}
};
};
@@ -150,7 +150,7 @@
{
uint32_t val = std::is_signed_v<Integer> ?
sext<sizeof(Integer) * 8>(i) : i;
- tc->setIntReg(ArmISA::INTREG_R0, val);
+ tc->setReg(ArmISA::int_reg::R0, val);
}
};
@@ -161,7 +161,7 @@
static void
store(ThreadContext *tc, const Integer &i)
{
- tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)i);
+ tc->setReg(ArmISA::int_reg::R0, (uint32_t)i);
}
};
@@ -173,11 +173,11 @@
store(ThreadContext *tc, const Integer &i)
{
if (ArmISA::byteOrder(tc) == ByteOrder::little) {
- tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)(i >> 0));
- tc->setIntReg(ArmISA::INTREG_R1, (uint32_t)(i >> 32));
+ tc->setReg(ArmISA::int_reg::R0, (uint32_t)(i >> 0));
+ tc->setReg(ArmISA::int_reg::R1, (uint32_t)(i >> 32));
} else {
- tc->setIntReg(ArmISA::INTREG_R0, (uint32_t)(i >> 32));
- tc->setIntReg(ArmISA::INTREG_R1, (uint32_t)(i >> 0));
+ tc->setReg(ArmISA::int_reg::R0, (uint32_t)(i >> 32));
+ tc->setReg(ArmISA::int_reg::R1, (uint32_t)(i >> 0));
}
}
};
@@ -191,7 +191,7 @@
get(ThreadContext *tc, Aapcs32::State &state)
{
if (state.ncrn <= state.MAX_CRN) {
- return tc->readIntReg(state.ncrn++);
+ return tc->getReg(RegId(IntRegClass, state.ncrn++));
}
// Max out the ncrn since we effectively exhausted it.
@@ -216,11 +216,11 @@
state.ncrn + 1 <= state.MAX_CRN) {
Integer low, high;
if (ArmISA::byteOrder(tc) == ByteOrder::little) {
- low = tc->readIntReg(state.ncrn++) & mask(32);
- high = tc->readIntReg(state.ncrn++) & mask(32);
+ low = tc->getReg(RegId(IntRegClass, state.ncrn++)) & mask(32);
+ high = tc->getReg(RegId(IntRegClass, state.ncrn++)) & mask(32);
} else {
- high = tc->readIntReg(state.ncrn++) & mask(32);
- low = tc->readIntReg(state.ncrn++) & mask(32);
+ high = tc->getReg(RegId(IntRegClass, state.ncrn++)) & mask(32);
+ low = tc->getReg(RegId(IntRegClass, state.ncrn++)) & mask(32);
}
return low | (high << 32);
}
@@ -284,7 +284,7 @@
uint32_t val;
memcpy((void *)&val, (void *)&cp, sizeof(Composite));
val = gtoh(val, ArmISA::byteOrder(tc));
- tc->setIntReg(ArmISA::INTREG_R0, val);
+ tc->setReg(ArmISA::int_reg::R0, val);
} else {
VPtr<Composite> cp(state.retAddr, tc);
*cp = htog(composite, ArmISA::byteOrder(tc));
@@ -295,7 +295,7 @@
prepare(ThreadContext *tc, Aapcs32::State &state)
{
if (sizeof(Composite) > sizeof(uint32_t))
- state.retAddr = tc->readIntReg(state.ncrn++);
+ state.retAddr = tc->getReg(RegId(IntRegClass, state.ncrn++));
}
};
@@ -316,7 +316,7 @@
if (bytes <= chunk_size) {
if (state.ncrn++ <= state.MAX_CRN) {
alignas(alignof(Composite)) uint32_t val =
- tc->readIntReg(state.ncrn++);
+ tc->getReg(RegId(IntRegClass, state.ncrn++));
val = htog(val, ArmISA::byteOrder(tc));
return gtoh(*(Composite *)&val, ArmISA::byteOrder(tc));
}
@@ -328,7 +328,7 @@
if (state.ncrn + regs - 1 <= state.MAX_CRN) {
alignas(alignof(Composite)) uint8_t buf[bytes];
for (int i = 0; i < regs; i++) {
- Chunk val = tc->readIntReg(state.ncrn++);
+ Chunk val = tc->getReg(RegId(IntRegClass, state.ncrn++));
val = htog(val, ArmISA::byteOrder(tc));
size_t to_copy = std::min<size_t>(bytes, chunk_size);
memcpy(buf + i * chunk_size, &val, to_copy);
@@ -342,7 +342,7 @@
int offset = 0;
while (state.ncrn <= state.MAX_CRN) {
- Chunk val = tc->readIntReg(state.ncrn++);
+ Chunk val = tc->getReg(RegId(IntRegClass, state.ncrn++));
val = htog(val, ArmISA::byteOrder(tc));
size_t to_copy = std::min<size_t>(bytes, chunk_size);
memcpy(buf + offset, &val, to_copy);
diff --git a/src/arch/arm/aapcs64.hh b/src/arch/arm/aapcs64.hh
index 7f2d162..3398d40 100644
--- a/src/arch/arm/aapcs64.hh
+++ b/src/arch/arm/aapcs64.hh
@@ -61,7 +61,7 @@
static const int MAX_SRN = 7;
explicit State(const ThreadContext *tc) :
- nsaa(tc->readIntReg(ArmISA::INTREG_SPX))
+ nsaa(tc->getReg(ArmISA::int_reg::Spx))
{}
};
};
@@ -238,7 +238,7 @@
get(ThreadContext *tc, Aapcs64::State &state)
{
if (state.ngrn <= state.MAX_GRN)
- return tc->readIntReg(state.ngrn++);
+ return tc->getReg(RegId(IntRegClass, state.ngrn++));
// Max out ngrn since we've effectively saturated it.
state.ngrn = state.MAX_GRN + 1;
@@ -259,8 +259,8 @@
state.ngrn++;
if (sizeof(Integer) == 16 && state.ngrn + 1 <= state.MAX_GRN) {
- Integer low = tc->readIntReg(state.ngrn++);
- Integer high = tc->readIntReg(state.ngrn++);
+ Integer low = tc->getReg(RegId(IntRegClass, state.ngrn++));
+ Integer high = tc->getReg(RegId(IntRegClass, state.ngrn++));
high = high << 64;
return high | low;
}
@@ -279,7 +279,7 @@
static void
store(ThreadContext *tc, const Integer &i)
{
- tc->setIntReg(0, i);
+ tc->setReg(ArmISA::int_reg::X0, i);
}
};
@@ -290,8 +290,8 @@
static void
store(ThreadContext *tc, const Integer &i)
{
- tc->setIntReg(0, (uint64_t)i);
- tc->setIntReg(1, (uint64_t)(i >> 64));
+ tc->setReg(ArmISA::int_reg::X0, (uint64_t)i);
+ tc->setReg(ArmISA::int_reg::X1, (uint64_t)(i >> 64));
}
};
@@ -379,7 +379,7 @@
if (state.ngrn + regs - 1 <= state.MAX_GRN) {
alignas(alignof(Composite)) uint8_t buf[bytes];
for (int i = 0; i < regs; i++) {
- Chunk val = tc->readIntReg(state.ngrn++);
+ Chunk val = tc->getReg(RegId(IntRegClass, state.ngrn++));
val = htog(val, ArmISA::byteOrder(tc));
size_t to_copy = std::min<size_t>(bytes, chunk_size);
memcpy(buf + i * chunk_size, &val, to_copy);
@@ -403,7 +403,7 @@
store(ThreadContext *tc, const Composite &c)
{
if (sizeof(Composite) > 16) {
- Addr addr = tc->readIntReg(ArmISA::INTREG_X8);
+ Addr addr = tc->getReg(ArmISA::int_reg::X8);
VPtr<Composite> composite(addr, tc);
*composite = htog(c, ArmISA::byteOrder(tc));
return;
@@ -426,7 +426,7 @@
memcpy(&val, buf, to_copy);
val = gtoh(val, ArmISA::byteOrder(tc));
- tc->setIntReg(i, val);
+ tc->setReg(ArmISA::int_reg::x(i), val);
bytes -= to_copy;
buf += to_copy;
diff --git a/src/arch/arm/fastmodel/CortexA76/thread_context.cc b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
index 36c6458..82b45c0 100644
--- a/src/arch/arm/fastmodel/CortexA76/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexA76/thread_context.cc
@@ -102,7 +102,7 @@
auto *non_const_this = const_cast<CortexA76TC *>(this);
- if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
+ if (idx == ArmISA::int_reg::R13Mon || idx == ArmISA::int_reg::R14Mon) {
orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
ArmISA::CPSR new_cpsr = orig_cpsr;
new_cpsr.mode = ArmISA::MODE_MON;
@@ -111,7 +111,7 @@
RegVal val = ThreadContext::readIntRegFlat(idx);
- if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
+ if (idx == ArmISA::int_reg::R13Mon || idx == ArmISA::int_reg::R14Mon) {
non_const_this->setMiscReg(ArmISA::MISCREG_CPSR, orig_cpsr);
}
@@ -123,7 +123,7 @@
{
ArmISA::CPSR orig_cpsr;
- if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
+ if (idx == ArmISA::int_reg::R13Mon || idx == ArmISA::int_reg::R14Mon) {
orig_cpsr = readMiscRegNoEffect(ArmISA::MISCREG_CPSR);
ArmISA::CPSR new_cpsr = orig_cpsr;
new_cpsr.mode = ArmISA::MODE_MON;
@@ -132,7 +132,7 @@
ThreadContext::setIntRegFlat(idx, val);
- if (idx == ArmISA::INTREG_R13_MON || idx == ArmISA::INTREG_R14_MON) {
+ if (idx == ArmISA::int_reg::R13Mon || idx == ArmISA::int_reg::R14Mon) {
setMiscReg(ArmISA::MISCREG_CPSR, orig_cpsr);
}
}
@@ -832,99 +832,99 @@
});
Iris::ThreadContext::IdxNameMap CortexA76TC::intReg32IdxNameMap({
- { ArmISA::INTREG_R0, "R0" },
- { ArmISA::INTREG_R1, "R1" },
- { ArmISA::INTREG_R2, "R2" },
- { ArmISA::INTREG_R3, "R3" },
- { ArmISA::INTREG_R4, "R4" },
- { ArmISA::INTREG_R5, "R5" },
- { ArmISA::INTREG_R6, "R6" },
- { ArmISA::INTREG_R7, "R7" },
- { ArmISA::INTREG_R8, "R8" },
- { ArmISA::INTREG_R9, "R9" },
- { ArmISA::INTREG_R10, "R10" },
- { ArmISA::INTREG_R11, "R11" },
- { ArmISA::INTREG_R12, "R12" },
- { ArmISA::INTREG_R13, "R13" },
- { ArmISA::INTREG_R14, "R14" },
- { ArmISA::INTREG_R15, "R15" }
+ { ArmISA::int_reg::R0, "R0" },
+ { ArmISA::int_reg::R1, "R1" },
+ { ArmISA::int_reg::R2, "R2" },
+ { ArmISA::int_reg::R3, "R3" },
+ { ArmISA::int_reg::R4, "R4" },
+ { ArmISA::int_reg::R5, "R5" },
+ { ArmISA::int_reg::R6, "R6" },
+ { ArmISA::int_reg::R7, "R7" },
+ { ArmISA::int_reg::R8, "R8" },
+ { ArmISA::int_reg::R9, "R9" },
+ { ArmISA::int_reg::R10, "R10" },
+ { ArmISA::int_reg::R11, "R11" },
+ { ArmISA::int_reg::R12, "R12" },
+ { ArmISA::int_reg::R13, "R13" },
+ { ArmISA::int_reg::R14, "R14" },
+ { ArmISA::int_reg::R15, "R15" }
});
Iris::ThreadContext::IdxNameMap CortexA76TC::intReg64IdxNameMap({
- { ArmISA::INTREG_X0, "X0" },
- { ArmISA::INTREG_X1, "X1" },
- { ArmISA::INTREG_X2, "X2" },
- { ArmISA::INTREG_X3, "X3" },
- { ArmISA::INTREG_X4, "X4" },
- { ArmISA::INTREG_X5, "X5" },
- { ArmISA::INTREG_X6, "X6" },
- { ArmISA::INTREG_X7, "X7" },
- { ArmISA::INTREG_X8, "X8" },
- { ArmISA::INTREG_X9, "X9" },
- { ArmISA::INTREG_X10, "X10" },
- { ArmISA::INTREG_X11, "X11" },
- { ArmISA::INTREG_X12, "X12" },
- { ArmISA::INTREG_X13, "X13" },
- { ArmISA::INTREG_X14, "X14" },
- { ArmISA::INTREG_X15, "X15" },
- { ArmISA::INTREG_X16, "X16" },
- { ArmISA::INTREG_X17, "X17" },
- { ArmISA::INTREG_X18, "X18" },
- { ArmISA::INTREG_X19, "X19" },
- { ArmISA::INTREG_X20, "X20" },
- { ArmISA::INTREG_X21, "X21" },
- { ArmISA::INTREG_X22, "X22" },
- { ArmISA::INTREG_X23, "X23" },
- { ArmISA::INTREG_X24, "X24" },
- { ArmISA::INTREG_X25, "X25" },
- { ArmISA::INTREG_X26, "X26" },
- { ArmISA::INTREG_X27, "X27" },
- { ArmISA::INTREG_X28, "X28" },
- { ArmISA::INTREG_X29, "X29" },
- { ArmISA::INTREG_X30, "X30" },
- { ArmISA::INTREG_SPX, "SP" },
+ { ArmISA::int_reg::X0, "X0" },
+ { ArmISA::int_reg::X1, "X1" },
+ { ArmISA::int_reg::X2, "X2" },
+ { ArmISA::int_reg::X3, "X3" },
+ { ArmISA::int_reg::X4, "X4" },
+ { ArmISA::int_reg::X5, "X5" },
+ { ArmISA::int_reg::X6, "X6" },
+ { ArmISA::int_reg::X7, "X7" },
+ { ArmISA::int_reg::X8, "X8" },
+ { ArmISA::int_reg::X9, "X9" },
+ { ArmISA::int_reg::X10, "X10" },
+ { ArmISA::int_reg::X11, "X11" },
+ { ArmISA::int_reg::X12, "X12" },
+ { ArmISA::int_reg::X13, "X13" },
+ { ArmISA::int_reg::X14, "X14" },
+ { ArmISA::int_reg::X15, "X15" },
+ { ArmISA::int_reg::X16, "X16" },
+ { ArmISA::int_reg::X17, "X17" },
+ { ArmISA::int_reg::X18, "X18" },
+ { ArmISA::int_reg::X19, "X19" },
+ { ArmISA::int_reg::X20, "X20" },
+ { ArmISA::int_reg::X21, "X21" },
+ { ArmISA::int_reg::X22, "X22" },
+ { ArmISA::int_reg::X23, "X23" },
+ { ArmISA::int_reg::X24, "X24" },
+ { ArmISA::int_reg::X25, "X25" },
+ { ArmISA::int_reg::X26, "X26" },
+ { ArmISA::int_reg::X27, "X27" },
+ { ArmISA::int_reg::X28, "X28" },
+ { ArmISA::int_reg::X29, "X29" },
+ { ArmISA::int_reg::X30, "X30" },
+ { ArmISA::int_reg::Spx, "SP" },
});
Iris::ThreadContext::IdxNameMap CortexA76TC::flattenedIntIdxNameMap({
- { ArmISA::INTREG_R0, "X0" },
- { ArmISA::INTREG_R1, "X1" },
- { ArmISA::INTREG_R2, "X2" },
- { ArmISA::INTREG_R3, "X3" },
- { ArmISA::INTREG_R4, "X4" },
- { ArmISA::INTREG_R5, "X5" },
- { ArmISA::INTREG_R6, "X6" },
- { ArmISA::INTREG_R7, "X7" },
- { ArmISA::INTREG_R8, "X8" },
- { ArmISA::INTREG_R9, "X9" },
- { ArmISA::INTREG_R10, "X10" },
- { ArmISA::INTREG_R11, "X11" },
- { ArmISA::INTREG_R12, "X12" },
- { ArmISA::INTREG_R13, "X13" },
- { ArmISA::INTREG_R14, "X14" },
+ { ArmISA::int_reg::R0, "X0" },
+ { ArmISA::int_reg::R1, "X1" },
+ { ArmISA::int_reg::R2, "X2" },
+ { ArmISA::int_reg::R3, "X3" },
+ { ArmISA::int_reg::R4, "X4" },
+ { ArmISA::int_reg::R5, "X5" },
+ { ArmISA::int_reg::R6, "X6" },
+ { ArmISA::int_reg::R7, "X7" },
+ { ArmISA::int_reg::R8, "X8" },
+ { ArmISA::int_reg::R9, "X9" },
+ { ArmISA::int_reg::R10, "X10" },
+ { ArmISA::int_reg::R11, "X11" },
+ { ArmISA::int_reg::R12, "X12" },
+ { ArmISA::int_reg::R13, "X13" },
+ { ArmISA::int_reg::R14, "X14" },
// Skip PC.
- { ArmISA::INTREG_R13_SVC, "X19" },
- { ArmISA::INTREG_R14_SVC, "X18" },
- { ArmISA::INTREG_R13_MON, "R13" }, // Need to be in monitor mode?
- { ArmISA::INTREG_R14_MON, "R14" }, // Need to be in monitor mode?
- { ArmISA::INTREG_R13_HYP, "X15" },
- { ArmISA::INTREG_R13_ABT, "X21" },
- { ArmISA::INTREG_R14_ABT, "X20" },
- { ArmISA::INTREG_R13_UND, "X23" },
- { ArmISA::INTREG_R14_UND, "X22" },
- { ArmISA::INTREG_R13_IRQ, "X17" },
- { ArmISA::INTREG_R14_IRQ, "X16" },
- { ArmISA::INTREG_R8_FIQ, "X24" },
- { ArmISA::INTREG_R9_FIQ, "X25" },
- { ArmISA::INTREG_R10_FIQ, "X26" },
- { ArmISA::INTREG_R11_FIQ, "X27" },
- { ArmISA::INTREG_R12_FIQ, "X28" },
- { ArmISA::INTREG_R13_FIQ, "X29" },
- { ArmISA::INTREG_R14_FIQ, "X30" },
+ { ArmISA::int_reg::R13Svc, "X19" },
+ { ArmISA::int_reg::R14Svc, "X18" },
+ { ArmISA::int_reg::R13Mon, "R13" }, // Need to be in monitor mode?
+ { ArmISA::int_reg::R14Mon, "R14" }, // Need to be in monitor mode?
+ { ArmISA::int_reg::R13Hyp, "X15" },
+ { ArmISA::int_reg::R13Abt, "X21" },
+ { ArmISA::int_reg::R14Abt, "X20" },
+ { ArmISA::int_reg::R13Und, "X23" },
+ { ArmISA::int_reg::R14Und, "X22" },
+ { ArmISA::int_reg::R13Irq, "X17" },
+ { ArmISA::int_reg::R14Irq, "X16" },
+ { ArmISA::int_reg::R8Fiq, "X24" },
+ { ArmISA::int_reg::R9Fiq, "X25" },
+ { ArmISA::int_reg::R10Fiq, "X26" },
+ { ArmISA::int_reg::R11Fiq, "X27" },
+ { ArmISA::int_reg::R12Fiq, "X28" },
+ { ArmISA::int_reg::R13Fiq, "X29" },
+ { ArmISA::int_reg::R14Fiq, "X30" },
// Skip zero, ureg0-2, and dummy regs.
- { ArmISA::INTREG_SP0, "SP_EL0" },
- { ArmISA::INTREG_SP1, "SP_EL1" },
- { ArmISA::INTREG_SP2, "SP_EL2" },
- { ArmISA::INTREG_SP3, "SP_EL3" },
+ { ArmISA::int_reg::Sp0, "SP_EL0" },
+ { ArmISA::int_reg::Sp1, "SP_EL1" },
+ { ArmISA::int_reg::Sp2, "SP_EL2" },
+ { ArmISA::int_reg::Sp3, "SP_EL3" },
});
Iris::ThreadContext::IdxNameMap CortexA76TC::ccRegIdxNameMap({
diff --git a/src/arch/arm/fastmodel/CortexR52/thread_context.cc b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
index 269baf5..6afd6f3 100644
--- a/src/arch/arm/fastmodel/CortexR52/thread_context.cc
+++ b/src/arch/arm/fastmodel/CortexR52/thread_context.cc
@@ -792,22 +792,22 @@
});
Iris::ThreadContext::IdxNameMap CortexR52TC::intReg32IdxNameMap({
- { ArmISA::INTREG_R0, "R0" },
- { ArmISA::INTREG_R1, "R1" },
- { ArmISA::INTREG_R2, "R2" },
- { ArmISA::INTREG_R3, "R3" },
- { ArmISA::INTREG_R4, "R4" },
- { ArmISA::INTREG_R5, "R5" },
- { ArmISA::INTREG_R6, "R6" },
- { ArmISA::INTREG_R7, "R7" },
- { ArmISA::INTREG_R8, "R8" },
- { ArmISA::INTREG_R9, "R9" },
- { ArmISA::INTREG_R10, "R10" },
- { ArmISA::INTREG_R11, "R11" },
- { ArmISA::INTREG_R12, "R12" },
- { ArmISA::INTREG_R13, "R13" },
- { ArmISA::INTREG_R14, "R14" },
- { ArmISA::INTREG_R15, "R15" }
+ { ArmISA::int_reg::R0, "R0" },
+ { ArmISA::int_reg::R1, "R1" },
+ { ArmISA::int_reg::R2, "R2" },
+ { ArmISA::int_reg::R3, "R3" },
+ { ArmISA::int_reg::R4, "R4" },
+ { ArmISA::int_reg::R5, "R5" },
+ { ArmISA::int_reg::R6, "R6" },
+ { ArmISA::int_reg::R7, "R7" },
+ { ArmISA::int_reg::R8, "R8" },
+ { ArmISA::int_reg::R9, "R9" },
+ { ArmISA::int_reg::R10, "R10" },
+ { ArmISA::int_reg::R11, "R11" },
+ { ArmISA::int_reg::R12, "R12" },
+ { ArmISA::int_reg::R13, "R13" },
+ { ArmISA::int_reg::R14, "R14" },
+ { ArmISA::int_reg::R15, "R15" }
});
Iris::ThreadContext::IdxNameMap CortexR52TC::ccRegIdxNameMap({
diff --git a/src/arch/arm/faults.cc b/src/arch/arm/faults.cc
index 8564147..947efbe 100644
--- a/src/arch/arm/faults.cc
+++ b/src/arch/arm/faults.cc
@@ -582,7 +582,7 @@
tc->setMiscReg(MISCREG_ELR_HYP, cur_pc +
(saved_cpsr.t ? thumbPcOffset(true) : armPcOffset(true)));
} else {
- tc->setIntReg(INTREG_LR, cur_pc +
+ tc->setReg(int_reg::Lr, cur_pc +
(saved_cpsr.t ? thumbPcOffset(false) : armPcOffset(false)));
}
@@ -619,7 +619,7 @@
Addr new_pc = getVector(tc);
DPRINTF(Faults, "Invoking Fault:%s cpsr:%#x PC:%#x lr:%#x newVec: %#x "
- "%s\n", name(), cpsr, cur_pc, tc->readIntReg(INTREG_LR),
+ "%s\n", name(), cpsr, cur_pc, tc->getReg(int_reg::Lr),
new_pc, arm_inst ? csprintf("inst: %#x", arm_inst->encoding()) :
std::string());
PCState pc(new_pc);
diff --git a/src/arch/arm/freebsd/fs_workload.cc b/src/arch/arm/freebsd/fs_workload.cc
index fe04fd4..5e6b954 100644
--- a/src/arch/arm/freebsd/fs_workload.cc
+++ b/src/arch/arm/freebsd/fs_workload.cc
@@ -115,9 +115,9 @@
// Kernel boot requirements to set up r0, r1 and r2 in ARMv7
for (auto *tc: system->threads) {
- tc->setIntReg(0, 0);
- tc->setIntReg(1, params().machine_type);
- tc->setIntReg(2, params().dtb_addr);
+ tc->setReg(int_reg::R0, (RegVal)0);
+ tc->setReg(int_reg::R1, params().machine_type);
+ tc->setReg(int_reg::R2, params().dtb_addr);
}
}
diff --git a/src/arch/arm/freebsd/se_workload.cc b/src/arch/arm/freebsd/se_workload.cc
index 66e587e..b8b222d 100644
--- a/src/arch/arm/freebsd/se_workload.cc
+++ b/src/arch/arm/freebsd/se_workload.cc
@@ -157,9 +157,9 @@
process->Process::syscall(tc);
if (dynamic_cast<ArmProcess64 *>(process))
- syscallDescs64.get(tc->readIntReg(INTREG_X8))->doSyscall(tc);
+ syscallDescs64.get(tc->getReg(int_reg::X8))->doSyscall(tc);
else
- syscallDescs32.get(tc->readIntReg(INTREG_R7))->doSyscall(tc);
+ syscallDescs32.get(tc->getReg(int_reg::R7))->doSyscall(tc);
}
} // namespace ArmISA
diff --git a/src/arch/arm/freebsd/se_workload.hh b/src/arch/arm/freebsd/se_workload.hh
index 4ec5090..93af483 100644
--- a/src/arch/arm/freebsd/se_workload.hh
+++ b/src/arch/arm/freebsd/se_workload.hh
@@ -90,9 +90,9 @@
tc->setCCReg(ArmISA::CCREG_C, 1);
val = ret.encodedValue();
}
- tc->setIntReg(ArmISA::ReturnValueReg, val);
+ tc->setReg(ArmISA::ReturnValueReg, val);
if (ret.count() > 1)
- tc->setIntReg(ArmISA::SyscallPseudoReturnReg, ret.value2());
+ tc->setReg(ArmISA::SyscallPseudoReturnReg, ret.value2());
}
};
diff --git a/src/arch/arm/fs_workload.cc b/src/arch/arm/fs_workload.cc
index 6a79aa0..367db20 100644
--- a/src/arch/arm/fs_workload.cc
+++ b/src/arch/arm/fs_workload.cc
@@ -59,9 +59,9 @@
{
PCState new_pc = tc->pcState().as<PCState>();
if (inAArch64(tc)) {
- new_pc.set(tc->readIntReg(INTREG_X30));
+ new_pc.set(tc->getReg(int_reg::X30));
} else {
- new_pc.set(tc->readIntReg(ReturnAddressReg) & ~1ULL);
+ new_pc.set(tc->getReg(ReturnAddressReg) & ~1ULL);
}
CheckerCPU *checker = tc->getCheckerCpuPtr();
@@ -130,11 +130,11 @@
"gic_cpu_addr must be set with bootloader");
for (auto *tc: arm_sys->threads) {
- tc->setIntReg(3, kernelEntry);
+ tc->setReg(int_reg::R3, kernelEntry);
if (is_gic_v2)
- tc->setIntReg(4, arm_sys->params().gic_cpu_addr);
+ tc->setReg(int_reg::R4, arm_sys->params().gic_cpu_addr);
if (getArch() == loader::Arm)
- tc->setIntReg(5, params().cpu_release_addr);
+ tc->setReg(int_reg::R5, params().cpu_release_addr);
}
inform("Using kernel entry physical address at %#x\n", kernelEntry);
} else {
@@ -144,7 +144,7 @@
}
}
- loader::ObjectFile *
+loader::ObjectFile *
FsWorkload::getBootLoader(loader::ObjectFile *const obj)
{
if (obj) {
diff --git a/src/arch/arm/htm.cc b/src/arch/arm/htm.cc
index 8d20563..534fd8d 100644
--- a/src/arch/arm/htm.cc
+++ b/src/arch/arm/htm.cc
@@ -71,13 +71,13 @@
void
ArmISA::HTMCheckpoint::save(ThreadContext *tc)
{
- sp = tc->readIntReg(INTREG_SPX);
+ sp = tc->getReg(int_reg::Spx);
// below should be enabled on condition that GICV3 is enabled
//tme_checkpoint->iccPmrEl1 = tc->readMiscReg(MISCREG_ICC_PMR_EL1);
nzcv = tc->readMiscReg(MISCREG_NZCV);
daif = tc->readMiscReg(MISCREG_DAIF);
- for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
- x[n] = tc->readIntReg(n);
+ for (auto n = 0; n < int_reg::NumArchRegs; n++) {
+ x[n] = tc->getReg(RegId(IntRegClass, n));
}
// TODO first detect if FP is enabled at this EL
for (auto n = 0; n < NumVecRegs; n++) {
@@ -98,13 +98,13 @@
void
ArmISA::HTMCheckpoint::restore(ThreadContext *tc, HtmFailureFaultCause cause)
{
- tc->setIntReg(INTREG_SPX, sp);
+ tc->setReg(int_reg::Spx, sp);
// below should be enabled on condition that GICV3 is enabled
//tc->setMiscReg(MISCREG_ICC_PMR_EL1, tme_checkpoint->iccPmrEl1);
tc->setMiscReg(MISCREG_NZCV, nzcv);
tc->setMiscReg(MISCREG_DAIF, daif);
- for (auto n = 0; n < NUM_ARCH_INTREGS; n++) {
- tc->setIntReg(n, x[n]);
+ for (auto n = 0; n < int_reg::NumArchRegs; n++) {
+ tc->setReg(RegId(IntRegClass, n), x[n]);
}
// TODO first detect if FP is enabled at this EL
for (auto n = 0; n < NumVecRegs; n++) {
@@ -158,7 +158,7 @@
replaceBits(error_code, 15, 1);
if (interrupt)
replaceBits(error_code, 23, 1);
- tc->setIntReg(rt, error_code);
+ tc->setReg(RegId(IntRegClass, rt), error_code);
// set next PC
pcstateckpt.uReset();
diff --git a/src/arch/arm/htm.hh b/src/arch/arm/htm.hh
index 7323687..2242bdc 100644
--- a/src/arch/arm/htm.hh
+++ b/src/arch/arm/htm.hh
@@ -74,7 +74,7 @@
private:
uint8_t rt; // TSTART destination register
Addr nPc; // Fallback instruction address
- std::array<RegVal, NUM_ARCH_INTREGS> x; // General purpose registers
+ std::array<RegVal, int_reg::NumArchRegs> x; // General purpose registers
std::array<VecRegContainer, NumVecRegs> z; // Vector registers
std::array<VecPredRegContainer, NumVecRegs> p; // Predicate registers
Addr sp; // Stack Pointer at current EL
diff --git a/src/arch/arm/insts/branch.hh b/src/arch/arm/insts/branch.hh
index 252fb50..56c60cb 100644
--- a/src/arch/arm/insts/branch.hh
+++ b/src/arch/arm/insts/branch.hh
@@ -82,11 +82,11 @@
class BranchReg : public PredOp
{
protected:
- IntRegIndex op1;
+ RegIndex op1;
public:
BranchReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1) :
+ RegIndex _op1) :
PredOp(mnem, _machInst, __opClass), op1(_op1)
{}
@@ -99,7 +99,7 @@
{
public:
BranchRegCond(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, ConditionCode _condCode) :
+ RegIndex _op1, ConditionCode _condCode) :
BranchReg(mnem, _machInst, __opClass, _op1)
{
// Only update if this isn't part of an IT block
@@ -112,12 +112,12 @@
class BranchRegReg : public PredOp
{
protected:
- IntRegIndex op1;
- IntRegIndex op2;
+ RegIndex op1;
+ RegIndex op2;
public:
BranchRegReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _op1, RegIndex _op2) :
PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
{}
@@ -130,11 +130,11 @@
{
protected:
int32_t imm;
- IntRegIndex op1;
+ RegIndex op1;
public:
BranchImmReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- int32_t _imm, IntRegIndex _op1) :
+ int32_t _imm, RegIndex _op1) :
PredOp(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
{}
};
diff --git a/src/arch/arm/insts/branch64.cc b/src/arch/arm/insts/branch64.cc
index 4c9552d..f4d0686 100644
--- a/src/arch/arm/insts/branch64.cc
+++ b/src/arch/arm/insts/branch64.cc
@@ -121,7 +121,7 @@
{
std::stringstream ss;
printMnemonic(ss, "", false);
- if (op1 != INTREG_X30)
+ if (op1 != int_reg::X30)
printIntReg(ss, op1);
return ss.str();
}
@@ -132,7 +132,7 @@
{
std::stringstream ss;
printMnemonic(ss, "", false);
- if (op1 != INTREG_X30)
+ if (op1 != int_reg::X30)
printIntReg(ss, op1);
return ss.str();
}
diff --git a/src/arch/arm/insts/branch64.hh b/src/arch/arm/insts/branch64.hh
index 551ade7..3babd70 100644
--- a/src/arch/arm/insts/branch64.hh
+++ b/src/arch/arm/insts/branch64.hh
@@ -87,12 +87,12 @@
class BranchRegReg64 : public ArmStaticInst
{
protected:
- IntRegIndex op1;
- IntRegIndex op2;
+ RegIndex op1;
+ RegIndex op2;
public:
BranchRegReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _op1, RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass), op1(_op1), op2(_op2)
{}
@@ -104,11 +104,11 @@
class BranchReg64 : public ArmStaticInst
{
protected:
- IntRegIndex op1;
+ RegIndex op1;
public:
BranchReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1) :
+ RegIndex _op1) :
ArmStaticInst(mnem, _machInst, __opClass), op1(_op1)
{}
@@ -121,7 +121,7 @@
{
public:
BranchRet64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1) :
+ RegIndex _op1) :
BranchReg64(mnem, _machInst, __opClass, _op1)
{}
@@ -134,7 +134,7 @@
{
public:
BranchRetA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- BranchRegReg64(mnem, _machInst, __opClass, INTREG_X30, INTREG_SPX)
+ BranchRegReg64(mnem, _machInst, __opClass, int_reg::X30, int_reg::Spx)
{}
std::string generateDisassembly(
@@ -157,11 +157,11 @@
class BranchEretA64 : public ArmStaticInst
{
protected:
- IntRegIndex op1;
+ RegIndex op1;
public:
BranchEretA64(const char *mnem, ExtMachInst _machInst, OpClass __opClass) :
- ArmStaticInst(mnem, _machInst, __opClass), op1(INTREG_SPX)
+ ArmStaticInst(mnem, _machInst, __opClass), op1(int_reg::Spx)
{}
std::string generateDisassembly(
@@ -172,11 +172,11 @@
{
protected:
int64_t imm;
- IntRegIndex op1;
+ RegIndex op1;
public:
BranchImmReg64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- int64_t _imm, IntRegIndex _op1) :
+ int64_t _imm, RegIndex _op1) :
ArmStaticInst(mnem, _machInst, __opClass), imm(_imm), op1(_op1)
{}
@@ -196,12 +196,12 @@
protected:
int64_t imm1;
int64_t imm2;
- IntRegIndex op1;
+ RegIndex op1;
public:
BranchImmImmReg64(const char *mnem, ExtMachInst _machInst,
OpClass __opClass, int64_t _imm1, int64_t _imm2,
- IntRegIndex _op1) :
+ RegIndex _op1) :
ArmStaticInst(mnem, _machInst, __opClass),
imm1(_imm1), imm2(_imm2), op1(_op1)
{}
diff --git a/src/arch/arm/insts/data64.cc b/src/arch/arm/insts/data64.cc
index 3c2a6c1..9efe54d 100644
--- a/src/arch/arm/insts/data64.cc
+++ b/src/arch/arm/insts/data64.cc
@@ -49,7 +49,7 @@
{
std::stringstream ss;
printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
- INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
+ int_reg::Zero, int_reg::Zero, 0, LSL, imm);
return ss.str();
}
@@ -70,7 +70,7 @@
{
std::stringstream ss;
printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
- op2, INTREG_ZERO, shiftAmt, shiftType, 0);
+ op2, int_reg::Zero, shiftAmt, shiftType, 0);
return ss.str();
}
@@ -80,7 +80,7 @@
{
std::stringstream ss;
printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
- op2, INTREG_ZERO, shiftAmt, LSL, 0);
+ op2, int_reg::Zero, shiftAmt, LSL, 0);
return ss.str();
}
diff --git a/src/arch/arm/insts/data64.hh b/src/arch/arm/insts/data64.hh
index d83602f..2dea9f1 100644
--- a/src/arch/arm/insts/data64.hh
+++ b/src/arch/arm/insts/data64.hh
@@ -50,11 +50,11 @@
class DataXImmOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
uint64_t imm;
DataXImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _dest, RegIndex _op1, uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
{}
@@ -66,11 +66,11 @@
class DataXImmOnlyOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
DataXImmOnlyOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, uint64_t _imm) :
+ RegIndex _dest, uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), imm(_imm)
{}
@@ -82,12 +82,12 @@
class DataXSRegOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
int32_t shiftAmt;
ArmShiftType shiftType;
DataXSRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2),
@@ -101,12 +101,12 @@
class DataXERegOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
ArmExtendType extendType;
int32_t shiftAmt;
DataXERegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
ArmExtendType _extendType, int32_t _shiftAmt) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2),
@@ -120,10 +120,10 @@
class DataX1RegOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
DataX1RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1) :
+ RegIndex _dest, RegIndex _op1) :
ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
{}
@@ -134,11 +134,11 @@
class DataX1RegImmOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
uint64_t imm;
DataX1RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _dest, RegIndex _op1, uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
imm(_imm)
{}
@@ -150,11 +150,11 @@
class DataX1Reg2ImmOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
uint64_t imm1, imm2;
DataX1Reg2ImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1,
+ RegIndex _dest, RegIndex _op1, uint64_t _imm1,
uint64_t _imm2) :
ArmStaticInst(mnem, _machInst, __opClass), dest(_dest), op1(_op1),
imm1(_imm1), imm2(_imm2)
@@ -167,10 +167,10 @@
class DataX2RegOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
DataX2RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
@@ -182,11 +182,11 @@
class DataX2RegImmOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
uint64_t imm;
DataX2RegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), imm(_imm)
@@ -199,11 +199,11 @@
class DataX3RegOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2, op3;
+ RegIndex dest, op1, op2, op3;
DataX3RegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _op3) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _op3) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), op3(_op3)
{}
@@ -215,13 +215,13 @@
class DataXCondCompImmOp : public ArmStaticInst
{
protected:
- IntRegIndex op1;
+ RegIndex op1;
uint64_t imm;
ConditionCode condCode;
uint8_t defCc;
DataXCondCompImmOp(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _op1, uint64_t _imm,
+ OpClass __opClass, RegIndex _op1, uint64_t _imm,
ConditionCode _condCode, uint8_t _defCc) :
ArmStaticInst(mnem, _machInst, __opClass),
op1(_op1), imm(_imm), condCode(_condCode), defCc(_defCc)
@@ -234,12 +234,12 @@
class DataXCondCompRegOp : public ArmStaticInst
{
protected:
- IntRegIndex op1, op2;
+ RegIndex op1, op2;
ConditionCode condCode;
uint8_t defCc;
DataXCondCompRegOp(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2,
+ OpClass __opClass, RegIndex _op1, RegIndex _op2,
ConditionCode _condCode, uint8_t _defCc) :
ArmStaticInst(mnem, _machInst, __opClass),
op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
@@ -252,11 +252,11 @@
class DataXCondSelOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
ConditionCode condCode;
DataXCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
ConditionCode _condCode) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
diff --git a/src/arch/arm/insts/macromem.cc b/src/arch/arm/insts/macromem.cc
index db274e5..effed08 100644
--- a/src/arch/arm/insts/macromem.cc
+++ b/src/arch/arm/insts/macromem.cc
@@ -55,7 +55,7 @@
{
MacroMemOp::MacroMemOp(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex rn,
+ OpClass __opClass, RegIndex rn,
bool index, bool up, bool user, bool writeback,
bool load, uint32_t reglist) :
PredMacroOp(mnem, machInst, __opClass)
@@ -98,13 +98,13 @@
// Add 0 to Rn and stick it in ureg0.
// This is equivalent to a move.
if (copy_base)
- *uop++ = new MicroAddiUop(machInst, INTREG_UREG0, rn, 0);
+ *uop++ = new MicroAddiUop(machInst, int_reg::Ureg0, rn, 0);
unsigned reg = 0;
while (mem_ops != 0) {
// Do load operations in pairs if possible
if (load && mem_ops >= 2 &&
- !(mem_ops == 2 && bits(regs,INTREG_PC) && exception_ret)) {
+ !(mem_ops == 2 && bits(regs, int_reg::Pc) && exception_ret)) {
// 64-bit memory operation
// Find 2 set register bits (clear them after finding)
unsigned reg_idx1;
@@ -113,22 +113,22 @@
// Find the first register
while (!bits(regs, reg)) reg++;
replaceBits(regs, reg, 0);
- reg_idx1 = force_user ? intRegInMode(MODE_USER, reg) : reg;
+ reg_idx1 = force_user ? int_reg::regInMode(MODE_USER, reg) : reg;
// Find the second register
while (!bits(regs, reg)) reg++;
replaceBits(regs, reg, 0);
- reg_idx2 = force_user ? intRegInMode(MODE_USER, reg) : reg;
+ reg_idx2 = force_user ? int_reg::regInMode(MODE_USER, reg) : reg;
// Load into temp reg if necessary
- if (reg_idx2 == INTREG_PC && pc_temp)
- reg_idx2 = INTREG_UREG1;
+ if (reg_idx2 == int_reg::Pc && pc_temp)
+ reg_idx2 = int_reg::Ureg1;
// Actually load both registers from memory
*uop = new MicroLdr2Uop(machInst, reg_idx1, reg_idx2,
- copy_base ? INTREG_UREG0 : rn, up, addr);
+ copy_base ? int_reg::Ureg0 : rn, up, addr);
- if (!writeback && reg_idx2 == INTREG_PC) {
+ if (!writeback && reg_idx2 == int_reg::Pc) {
// No writeback if idx==pc, set appropriate flags
(*uop)->setFlag(StaticInst::IsControl);
(*uop)->setFlag(StaticInst::IsIndirectControl);
@@ -148,27 +148,27 @@
unsigned reg_idx;
while (!bits(regs, reg)) reg++;
replaceBits(regs, reg, 0);
- reg_idx = force_user ? intRegInMode(MODE_USER, reg) : reg;
+ reg_idx = force_user ? int_reg::regInMode(MODE_USER, reg) : reg;
if (load) {
- if (writeback && reg_idx == INTREG_PC) {
+ if (writeback && reg_idx == int_reg::Pc) {
// If this instruction changes the PC and performs a
// writeback, ensure the pc load/branch is the last uop.
// Load into a temp reg here.
- *uop = new MicroLdrUop(machInst, INTREG_UREG1,
- copy_base ? INTREG_UREG0 : rn, up, addr);
- } else if (reg_idx == INTREG_PC && exception_ret) {
+ *uop = new MicroLdrUop(machInst, int_reg::Ureg1,
+ copy_base ? int_reg::Ureg0 : rn, up, addr);
+ } else if (reg_idx == int_reg::Pc && exception_ret) {
// Special handling for exception return
*uop = new MicroLdrRetUop(machInst, reg_idx,
- copy_base ? INTREG_UREG0 : rn, up, addr);
+ copy_base ? int_reg::Ureg0 : rn, up, addr);
} else {
// standard single load uop
*uop = new MicroLdrUop(machInst, reg_idx,
- copy_base ? INTREG_UREG0 : rn, up, addr);
+ copy_base ? int_reg::Ureg0 : rn, up, addr);
}
// Loading pc as last operation? Set appropriate flags.
- if (!writeback && reg_idx == INTREG_PC) {
+ if (!writeback && reg_idx == int_reg::Pc) {
(*uop)->setFlag(StaticInst::IsControl);
(*uop)->setFlag(StaticInst::IsIndirectControl);
@@ -200,9 +200,10 @@
// Write PC after address writeback?
if (pc_temp) {
if (exception_ret) {
- *uop = new MicroUopRegMovRet(machInst, 0, INTREG_UREG1);
+ *uop = new MicroUopRegMovRet(machInst, 0, int_reg::Ureg1);
} else {
- *uop = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG1);
+ *uop = new MicroUopRegMov(
+ machInst, int_reg::Pc, int_reg::Ureg1);
}
(*uop)->setFlag(StaticInst::IsControl);
(*uop)->setFlag(StaticInst::IsIndirectControl);
@@ -212,7 +213,7 @@
else
(*uop)->setFlag(StaticInst::IsUncondControl);
- if (rn == INTREG_SP)
+ if (rn == int_reg::Sp)
(*uop)->setFlag(StaticInst::IsReturn);
++uop;
@@ -244,7 +245,7 @@
uint32_t size, bool fp, bool load, bool noAlloc,
bool signExt, bool exclusive, bool acrel,
int64_t imm, AddrMode mode,
- IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) :
+ RegIndex rn, RegIndex rt, RegIndex rt2) :
PredMacroOp(mnem, machInst, __opClass)
{
bool post = (mode == AddrMd_PostIndex);
@@ -263,7 +264,7 @@
rn = makeSP(rn);
if (!post) {
- *uop++ = new MicroAddXiSpAlignUop(machInst, INTREG_UREG0, rn,
+ *uop++ = new MicroAddXiSpAlignUop(machInst, int_reg::Ureg0, rn,
post ? 0 : imm);
}
@@ -271,67 +272,84 @@
if (size == 16) {
if (load) {
*uop++ = new MicroLdFp16Uop(machInst, rt,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
*uop++ = new MicroLdFp16Uop(machInst, rt2,
- post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 16, noAlloc, exclusive,
+ acrel);
} else {
*uop++ = new MicroStrQBFpXImmUop(machInst, rt,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
*uop++ = new MicroStrQTFpXImmUop(machInst, rt,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
*uop++ = new MicroStrQBFpXImmUop(machInst, rt2,
- post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 16, noAlloc, exclusive,
+ acrel);
*uop++ = new MicroStrQTFpXImmUop(machInst, rt2,
- post ? rn : INTREG_UREG0, 16, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 16, noAlloc, exclusive,
+ acrel);
}
} else if (size == 8) {
if (load) {
*uop++ = new MicroLdPairFp8Uop(machInst, rt, rt2,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
} else {
*uop++ = new MicroStrFpXImmUop(machInst, rt,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
*uop++ = new MicroStrFpXImmUop(machInst, rt2,
- post ? rn : INTREG_UREG0, 8, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 8, noAlloc, exclusive,
+ acrel);
}
} else if (size == 4) {
if (load) {
*uop++ = new MicroLdrDFpXImmUop(machInst, rt, rt2,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
} else {
*uop++ = new MicroStrDFpXImmUop(machInst, rt, rt2,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
}
}
} else {
if (size == 8) {
if (load) {
*uop++ = new MicroLdPairUop(machInst, rt, rt2,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
} else {
- *uop++ = new MicroStrXImmUop(machInst, rt, post ? rn : INTREG_UREG0,
- 0, noAlloc, exclusive, acrel);
- *uop++ = new MicroStrXImmUop(machInst, rt2, post ? rn : INTREG_UREG0,
- size, noAlloc, exclusive, acrel);
+ *uop++ = new MicroStrXImmUop(machInst, rt,
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
+ *uop++ = new MicroStrXImmUop(machInst, rt2,
+ post ? rn : int_reg::Ureg0, size, noAlloc, exclusive,
+ acrel);
}
} else if (size == 4) {
if (load) {
if (signExt) {
*uop++ = new MicroLdrDSXImmUop(machInst, rt, rt2,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
} else {
*uop++ = new MicroLdrDUXImmUop(machInst, rt, rt2,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
}
} else {
*uop++ = new MicroStrDXImmUop(machInst, rt, rt2,
- post ? rn : INTREG_UREG0, 0, noAlloc, exclusive, acrel);
+ post ? rn : int_reg::Ureg0, 0, noAlloc, exclusive,
+ acrel);
}
}
}
if (writeback) {
- *uop++ = new MicroAddXiUop(machInst, rn, post ? rn : INTREG_UREG0,
+ *uop++ = new MicroAddXiUop(machInst, rn, post ? rn : int_reg::Ureg0,
post ? imm : 0);
}
@@ -346,8 +364,8 @@
}
BigFpMemImmOp::BigFpMemImmOp(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, bool load, IntRegIndex dest,
- IntRegIndex base, int64_t imm) :
+ OpClass __opClass, bool load, RegIndex dest,
+ RegIndex base, int64_t imm) :
PredMacroOp(mnem, machInst, __opClass)
{
numMicroops = load ? 1 : 2;
@@ -367,8 +385,8 @@
}
BigFpMemPostOp::BigFpMemPostOp(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, bool load, IntRegIndex dest,
- IntRegIndex base, int64_t imm) :
+ OpClass __opClass, bool load, RegIndex dest,
+ RegIndex base, int64_t imm) :
PredMacroOp(mnem, machInst, __opClass)
{
numMicroops = load ? 2 : 3;
@@ -393,8 +411,8 @@
}
BigFpMemPreOp::BigFpMemPreOp(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, bool load, IntRegIndex dest,
- IntRegIndex base, int64_t imm) :
+ OpClass __opClass, bool load, RegIndex dest,
+ RegIndex base, int64_t imm) :
PredMacroOp(mnem, machInst, __opClass)
{
numMicroops = load ? 2 : 3;
@@ -419,8 +437,8 @@
}
BigFpMemRegOp::BigFpMemRegOp(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, bool load, IntRegIndex dest,
- IntRegIndex base, IntRegIndex offset,
+ OpClass __opClass, bool load, RegIndex dest,
+ RegIndex base, RegIndex offset,
ArmExtendType type, int64_t imm) :
PredMacroOp(mnem, machInst, __opClass)
{
@@ -445,7 +463,7 @@
}
BigFpMemLitOp::BigFpMemLitOp(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex dest,
+ OpClass __opClass, RegIndex dest,
int64_t imm) :
PredMacroOp(mnem, machInst, __opClass)
{
@@ -1125,8 +1143,8 @@
PredMacroOp(mnem, machInst, __opClass)
{
RegIndex vx = NumVecV8ArchRegs;
- RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
- bool baseIsSP = isSP((IntRegIndex) rnsp);
+ RegIndex rnsp = (RegIndex) makeSP((RegIndex) rn);
+ bool baseIsSP = isSP((RegIndex) rnsp);
numMicroops = wb ? 1 : 0;
@@ -1162,7 +1180,7 @@
// 64-bit general register OR as '11111' for an immediate value equal to
// the total number of bytes transferred (i.e. 8, 16, 24, 32, 48 or 64)
if (wb) {
- if (rm != ((RegIndex) INTREG_X31)) {
+ if (rm != int_reg::X31) {
microOps[uopIdx++] = new MicroAddXERegUop(machInst, rnsp, rnsp, rm,
UXTX, 0);
} else {
@@ -1210,8 +1228,8 @@
PredMacroOp(mnem, machInst, __opClass)
{
RegIndex vx = NumVecV8ArchRegs;
- RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
- bool baseIsSP = isSP((IntRegIndex) rnsp);
+ RegIndex rnsp = (RegIndex) makeSP((RegIndex) rn);
+ bool baseIsSP = isSP((RegIndex) rnsp);
numMicroops = wb ? 1 : 0;
@@ -1270,7 +1288,7 @@
// 64-bit general register OR as '11111' for an immediate value equal to
// the total number of bytes transferred (i.e. 8, 16, 24, 32, 48 or 64)
if (wb) {
- if (rm != ((RegIndex) INTREG_X31)) {
+ if (rm != int_reg::X31) {
microOps[uopIdx++] = new MicroAddXERegUop(machInst, rnsp, rnsp, rm,
UXTX, 0);
} else {
@@ -1299,8 +1317,8 @@
{
RegIndex vx = NumVecV8ArchRegs;
- RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
- bool baseIsSP = isSP((IntRegIndex) rnsp);
+ RegIndex rnsp = (RegIndex) makeSP((RegIndex) rn);
+ bool baseIsSP = isSP((RegIndex) rnsp);
numMicroops = wb ? 1 : 0;
@@ -1338,7 +1356,7 @@
// 64-bit general register OR as '11111' for an immediate value equal to
// the total number of bytes transferred (i.e. 8, 16, 24, 32, 48 or 64)
if (wb) {
- if (rm != ((RegIndex) INTREG_X31)) {
+ if (rm != int_reg::X31) {
microOps[uopIdx++] = new MicroAddXERegUop(machInst, rnsp, rnsp, rm,
UXTX, 0);
} else {
@@ -1372,8 +1390,8 @@
wb(false), replicate(false)
{
RegIndex vx = NumVecV8ArchRegs;
- RegIndex rnsp = (RegIndex) makeSP((IntRegIndex) rn);
- bool baseIsSP = isSP((IntRegIndex) rnsp);
+ RegIndex rnsp = (RegIndex) makeSP((RegIndex) rn);
+ bool baseIsSP = isSP((RegIndex) rnsp);
numMicroops = wb ? 1 : 0;
@@ -1417,7 +1435,7 @@
// 64-bit general register OR as '11111' for an immediate value equal to
// the total number of bytes transferred (i.e. 8, 16, 24, 32, 48 or 64)
if (wb) {
- if (rm != ((RegIndex) INTREG_X31)) {
+ if (rm != int_reg::X31) {
microOps[uopIdx++] = new MicroAddXERegUop(machInst, rnsp, rnsp, rm,
UXTX, 0);
} else {
@@ -1436,7 +1454,7 @@
}
MacroVFPMemOp::MacroVFPMemOp(const char *mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex rn,
+ OpClass __opClass, RegIndex rn,
RegIndex vd, bool single, bool up,
bool writeback, bool load, uint32_t offset) :
PredMacroOp(mnem, machInst, __opClass)
@@ -1560,7 +1578,7 @@
printIntReg(ss, ura);
ccprintf(ss, ", ");
printIntReg(ss, urb);
- printExtendOperand(false, ss, (IntRegIndex)urc, type, shiftAmt);
+ printExtendOperand(false, ss, (RegIndex)urc, type, shiftAmt);
return ss.str();
}
diff --git a/src/arch/arm/insts/macromem.hh b/src/arch/arm/insts/macromem.hh
index 90f12d2..429dced 100644
--- a/src/arch/arm/insts/macromem.hh
+++ b/src/arch/arm/insts/macromem.hh
@@ -287,10 +287,10 @@
class MicroSetPCCPSR : public MicroOp
{
protected:
- IntRegIndex ura, urb, urc;
+ RegIndex ura, urb, urc;
MicroSetPCCPSR(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex _ura, IntRegIndex _urb, IntRegIndex _urc)
+ RegIndex _ura, RegIndex _urb, RegIndex _urc)
: MicroOp(mnem, machInst, __opClass),
ura(_ura), urb(_urb), urc(_urc)
{
@@ -463,7 +463,7 @@
{
protected:
MacroMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex rn, bool index, bool up, bool user,
+ RegIndex rn, bool index, bool up, bool user,
bool writeback, bool load, uint32_t reglist);
};
@@ -484,43 +484,43 @@
PairMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
bool exclusive, bool acrel, int64_t imm, AddrMode mode,
- IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2);
+ RegIndex rn, RegIndex rt, RegIndex rt2);
};
class BigFpMemImmOp : public PredMacroOp
{
protected:
BigFpMemImmOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
+ bool load, RegIndex dest, RegIndex base, int64_t imm);
};
class BigFpMemPostOp : public PredMacroOp
{
protected:
BigFpMemPostOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
+ bool load, RegIndex dest, RegIndex base, int64_t imm);
};
class BigFpMemPreOp : public PredMacroOp
{
protected:
BigFpMemPreOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
+ bool load, RegIndex dest, RegIndex base, int64_t imm);
};
class BigFpMemRegOp : public PredMacroOp
{
protected:
BigFpMemRegOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- bool load, IntRegIndex dest, IntRegIndex base,
- IntRegIndex offset, ArmExtendType type, int64_t imm);
+ bool load, RegIndex dest, RegIndex base,
+ RegIndex offset, ArmExtendType type, int64_t imm);
};
class BigFpMemLitOp : public PredMacroOp
{
protected:
BigFpMemLitOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex dest, int64_t imm);
+ RegIndex dest, int64_t imm);
};
/**
@@ -570,7 +570,7 @@
{
protected:
MacroVFPMemOp(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex rn, RegIndex vd, bool single, bool up,
+ RegIndex rn, RegIndex vd, bool single, bool up,
bool writeback, bool load, uint32_t offset);
};
diff --git a/src/arch/arm/insts/mem.cc b/src/arch/arm/insts/mem.cc
index aed9933..590c30e 100644
--- a/src/arch/arm/insts/mem.cc
+++ b/src/arch/arm/insts/mem.cc
@@ -119,7 +119,7 @@
printMnemonic(ss, "ib");
break;
}
- printIntReg(ss, INTREG_SP);
+ printIntReg(ss, int_reg::Sp);
if (wb) {
ss << "!";
}
diff --git a/src/arch/arm/insts/mem.hh b/src/arch/arm/insts/mem.hh
index d5ef424..42dfac3 100644
--- a/src/arch/arm/insts/mem.hh
+++ b/src/arch/arm/insts/mem.hh
@@ -98,20 +98,20 @@
IncrementBefore
};
protected:
- IntRegIndex base;
+ RegIndex base;
AddrMode mode;
bool wb;
- IntRegIndex ura, urb, urc;
+ RegIndex ura, urb, urc;
static const unsigned numMicroops = 3;
StaticInstPtr *uops;
RfeOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _base, AddrMode _mode, bool _wb)
+ RegIndex _base, AddrMode _mode, bool _wb)
: MightBeMicro(mnem, _machInst, __opClass),
base(_base), mode(_mode), wb(_wb),
- ura(INTREG_UREG0), urb(INTREG_UREG1),
- urc(INTREG_UREG2),
+ ura(int_reg::Ureg0), urb(int_reg::Ureg1),
+ urc(int_reg::Ureg2),
uops(NULL)
{}
@@ -186,15 +186,15 @@
protected:
- IntRegIndex dest;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex base;
bool add;
static const unsigned numMicroops = 3;
StaticInstPtr *uops;
Memory(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _base, bool _add)
+ RegIndex _dest, RegIndex _base, bool _add)
: MightBeMicro(mnem, _machInst, __opClass),
dest(_dest), base(_base), add(_add), uops(NULL)
{}
@@ -232,7 +232,7 @@
int32_t imm;
MemoryImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _base, bool _add, int32_t _imm)
+ RegIndex _dest, RegIndex _base, bool _add, int32_t _imm)
: Memory(mnem, _machInst, __opClass, _dest, _base, _add), imm(_imm)
{}
@@ -249,10 +249,10 @@
class MemoryExImm : public MemoryImm
{
protected:
- IntRegIndex result;
+ RegIndex result;
MemoryExImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _result, IntRegIndex _dest, IntRegIndex _base,
+ RegIndex _result, RegIndex _dest, RegIndex _base,
bool _add, int32_t _imm)
: MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
result(_result)
@@ -271,11 +271,11 @@
class MemoryDImm : public MemoryImm
{
protected:
- IntRegIndex dest2;
+ RegIndex dest2;
MemoryDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: MemoryImm(mnem, _machInst, __opClass, _dest, _base, _add, _imm),
dest2(_dest2)
{}
@@ -292,11 +292,11 @@
class MemoryExDImm : public MemoryDImm
{
protected:
- IntRegIndex result;
+ RegIndex result;
MemoryExDImm(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ RegIndex _result, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: MemoryDImm(mnem, _machInst, __opClass, _dest, _dest2,
_base, _add, _imm), result(_result)
{}
@@ -316,12 +316,12 @@
protected:
int32_t shiftAmt;
ArmShiftType shiftType;
- IntRegIndex index;
+ RegIndex index;
MemoryReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _base, bool _add,
+ RegIndex _dest, RegIndex _base, bool _add,
int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: Memory(mnem, _machInst, __opClass, _dest, _base, _add),
shiftAmt(_shiftAmt), shiftType(_shiftType), index(_index)
{}
@@ -332,13 +332,13 @@
class MemoryDReg : public MemoryReg
{
protected:
- IntRegIndex dest2;
+ RegIndex dest2;
MemoryDReg(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add,
+ RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add,
int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: MemoryReg(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index),
dest2(_dest2)
@@ -358,38 +358,38 @@
{
protected:
MemoryOffset(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryOffset(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index)
{}
MemoryOffset(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ OpClass __opClass, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
{}
MemoryOffset(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _result,
- IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ OpClass __opClass, RegIndex _result,
+ RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _result,
_dest, _dest2, _base, _add, _imm)
{}
MemoryOffset(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add,
+ OpClass __opClass, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add,
int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index)
{}
@@ -409,38 +409,38 @@
{
protected:
MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index)
{}
MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ OpClass __opClass, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
{}
MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _result,
- IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ OpClass __opClass, RegIndex _result,
+ RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _result,
_dest, _dest2, _base, _add, _imm)
{}
MemoryPreIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add,
+ OpClass __opClass, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add,
int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index)
{}
@@ -460,38 +460,38 @@
{
protected:
MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _base, _add, _imm)
{}
MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
bool _add, int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _base, _add,
_shiftAmt, _shiftType, _index)
{}
MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ OpClass __opClass, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add, _imm)
{}
MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _result,
- IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add, int32_t _imm)
+ OpClass __opClass, RegIndex _result,
+ RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add, int32_t _imm)
: Base(mnem, _machInst, __opClass, _result,
_dest, _dest2, _base, _add, _imm)
{}
MemoryPostIndex(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, bool _add,
+ OpClass __opClass, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, bool _add,
int32_t _shiftAmt, ArmShiftType _shiftType,
- IntRegIndex _index)
+ RegIndex _index)
: Base(mnem, _machInst, __opClass, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index)
{}
diff --git a/src/arch/arm/insts/mem64.hh b/src/arch/arm/insts/mem64.hh
index 53c0527..da91887 100644
--- a/src/arch/arm/insts/mem64.hh
+++ b/src/arch/arm/insts/mem64.hh
@@ -52,7 +52,7 @@
class SysDC64 : public MiscRegOp64
{
protected:
- IntRegIndex base;
+ RegIndex base;
MiscRegIndex dest;
uint64_t imm;
@@ -60,7 +60,7 @@
mutable Addr faultAddr;
SysDC64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _base, MiscRegIndex _dest, uint64_t _imm)
+ RegIndex _base, MiscRegIndex _dest, uint64_t _imm)
: MiscRegOp64(mnem, _machInst, __opClass, false),
base(_base), dest(_dest), imm(_imm), faultAddr(0)
{}
@@ -116,8 +116,8 @@
protected:
- IntRegIndex dest;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex base;
/// True if the base register is SP (used for SP alignment checking).
bool baseIsSP;
static const unsigned numMicroops = 3;
@@ -125,7 +125,7 @@
StaticInstPtr *uops;
Memory64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _base)
+ RegIndex _dest, RegIndex _base)
: MightBeMicro64(mnem, _machInst, __opClass),
dest(_dest), base(_base), uops(NULL), memAccessFlags(0)
{
@@ -158,7 +158,7 @@
int64_t imm;
MemoryImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _base, int64_t _imm)
+ RegIndex _dest, RegIndex _base, int64_t _imm)
: Memory64(mnem, _machInst, __opClass, _dest, _base), imm(_imm)
{}
@@ -169,10 +169,10 @@
class MemoryDImm64 : public MemoryImm64
{
protected:
- IntRegIndex dest2;
+ RegIndex dest2;
MemoryDImm64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
+ RegIndex _dest, RegIndex _dest2, RegIndex _base,
int64_t _imm)
: MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm),
dest2(_dest2)
@@ -185,11 +185,11 @@
class MemoryDImmEx64 : public MemoryDImm64
{
protected:
- IntRegIndex result;
+ RegIndex result;
MemoryDImmEx64(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, int32_t _imm)
+ RegIndex _result, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, int32_t _imm)
: MemoryDImm64(mnem, _machInst, __opClass, _dest, _dest2,
_base, _imm), result(_result)
{}
@@ -202,7 +202,7 @@
{
protected:
MemoryPreIndex64(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
int64_t _imm)
: MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
{}
@@ -215,7 +215,7 @@
{
protected:
MemoryPostIndex64(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
int64_t _imm)
: MemoryImm64(mnem, _machInst, __opClass, _dest, _base, _imm)
{}
@@ -227,13 +227,13 @@
class MemoryReg64 : public Memory64
{
protected:
- IntRegIndex offset;
+ RegIndex offset;
ArmExtendType type;
uint64_t shiftAmt;
MemoryReg64(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
- IntRegIndex _offset, ArmExtendType _type,
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
+ RegIndex _offset, ArmExtendType _type,
uint64_t _shiftAmt)
: Memory64(mnem, _machInst, __opClass, _dest, _base),
offset(_offset), type(_type), shiftAmt(_shiftAmt)
@@ -247,7 +247,7 @@
{
protected:
MemoryRaw64(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base)
+ OpClass __opClass, RegIndex _dest, RegIndex _base)
: Memory64(mnem, _machInst, __opClass, _dest, _base)
{}
@@ -258,11 +258,11 @@
class MemoryEx64 : public Memory64
{
protected:
- IntRegIndex result;
+ RegIndex result;
MemoryEx64(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
- IntRegIndex _result)
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
+ RegIndex _result)
: Memory64(mnem, _machInst, __opClass, _dest, _base), result(_result)
{}
@@ -276,8 +276,8 @@
int64_t imm;
MemoryLiteral64(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, int64_t _imm)
- : Memory64(mnem, _machInst, __opClass, _dest, INTREG_ZERO), imm(_imm)
+ OpClass __opClass, RegIndex _dest, int64_t _imm)
+ : Memory64(mnem, _machInst, __opClass, _dest, int_reg::Zero), imm(_imm)
{}
std::string generateDisassembly(
@@ -287,17 +287,17 @@
class MemoryAtomicPair64 : public Memory64
{
protected:
- IntRegIndex dest2;
- IntRegIndex result;
- IntRegIndex result2;
+ RegIndex dest2;
+ RegIndex result;
+ RegIndex result2;
MemoryAtomicPair64(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _base,
- IntRegIndex _result)
+ OpClass __opClass, RegIndex _dest, RegIndex _base,
+ RegIndex _result)
: Memory64(mnem, _machInst, __opClass, _dest, _base),
- dest2((IntRegIndex)(_dest + (IntRegIndex)(1))),
+ dest2((RegIndex)(_dest + (RegIndex)(1))),
result(_result),
- result2((IntRegIndex)(_result + (IntRegIndex)(1)))
+ result2((RegIndex)(_result + (RegIndex)(1)))
{}
std::string generateDisassembly(
diff --git a/src/arch/arm/insts/misc.cc b/src/arch/arm/insts/misc.cc
index e9ddb1b..06a712e 100644
--- a/src/arch/arm/insts/misc.cc
+++ b/src/arch/arm/insts/misc.cc
@@ -339,7 +339,7 @@
printMnemonic(ss);
printIntReg(ss, dest);
ccprintf(ss, ", #%d, ", imm);
- printShiftOperand(ss, op1, true, shiftAmt, INTREG_ZERO, shiftType);
+ printShiftOperand(ss, op1, true, shiftAmt, int_reg::Zero, shiftType);
printIntReg(ss, op1);
return ss.str();
}
diff --git a/src/arch/arm/insts/misc.hh b/src/arch/arm/insts/misc.hh
index 49adf72..d9f24b9 100644
--- a/src/arch/arm/insts/misc.hh
+++ b/src/arch/arm/insts/misc.hh
@@ -46,10 +46,10 @@
class MrsOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
MrsOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
- ArmISA::IntRegIndex _dest) :
+ RegIndex _dest) :
ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest)
{}
@@ -87,10 +87,10 @@
class MsrRegOp : public MsrBase
{
protected:
- ArmISA::IntRegIndex op1;
+ RegIndex op1;
MsrRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _op1, uint8_t _byteMask) :
+ OpClass __opClass, RegIndex _op1, uint8_t _byteMask) :
MsrBase(mnem, _machInst, __opClass, _byteMask), op1(_op1)
{}
@@ -102,13 +102,13 @@
{
protected:
ArmISA::MiscRegIndex op1;
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex dest2;
+ RegIndex dest;
+ RegIndex dest2;
uint32_t imm;
MrrcOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
- ArmISA::MiscRegIndex _op1, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _dest2, uint32_t _imm) :
+ ArmISA::MiscRegIndex _op1, RegIndex _dest, RegIndex _dest2,
+ uint32_t _imm) :
ArmISA::PredOp(mnem, _machInst, __opClass), op1(_op1), dest(_dest),
dest2(_dest2), imm(_imm)
{}
@@ -120,13 +120,13 @@
class McrrOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex op1;
- ArmISA::IntRegIndex op2;
+ RegIndex op1;
+ RegIndex op2;
ArmISA::MiscRegIndex dest;
uint32_t imm;
McrrOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
- ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
+ RegIndex _op1, RegIndex _op2,
ArmISA::MiscRegIndex _dest, uint32_t _imm) :
ArmISA::PredOp(mnem, _machInst, __opClass), op1(_op1), op2(_op2),
dest(_dest), imm(_imm)
@@ -153,11 +153,11 @@
class RegImmOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
RegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm) :
+ OpClass __opClass, RegIndex _dest, uint64_t _imm) :
ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
{}
@@ -168,12 +168,12 @@
class RegRegOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
RegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1) :
ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
{}
@@ -184,10 +184,10 @@
class RegOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
RegOp(const char *mnem, ArmISA::ExtMachInst _machInst, OpClass __opClass,
- ArmISA::IntRegIndex _dest) :
+ RegIndex _dest) :
ArmISA::PredOp(mnem, _machInst, __opClass), dest(_dest)
{}
@@ -198,13 +198,13 @@
class RegImmRegOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
- ArmISA::IntRegIndex op1;
+ RegIndex op1;
RegImmRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest, uint64_t _imm,
- ArmISA::IntRegIndex _op1) :
+ OpClass __opClass, RegIndex _dest, uint64_t _imm,
+ RegIndex _op1) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), imm(_imm), op1(_op1)
{}
@@ -216,14 +216,14 @@
class RegRegRegImmOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
- ArmISA::IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
uint64_t imm;
RegRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), imm(_imm)
@@ -236,15 +236,15 @@
class RegRegRegRegOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
- ArmISA::IntRegIndex op2;
- ArmISA::IntRegIndex op3;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
+ RegIndex op3;
RegRegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
- ArmISA::IntRegIndex _op3) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
+ RegIndex _op3) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), op3(_op3)
{}
@@ -256,13 +256,13 @@
class RegRegRegOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
- ArmISA::IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
RegRegRegOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
@@ -274,13 +274,13 @@
class RegRegImmOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
uint64_t imm;
RegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1, uint64_t _imm) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
{}
@@ -293,12 +293,12 @@
{
protected:
ArmISA::MiscRegIndex dest;
- ArmISA::IntRegIndex op1;
+ RegIndex op1;
uint64_t imm;
MiscRegRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
OpClass __opClass, ArmISA::MiscRegIndex _dest,
- ArmISA::IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _op1, uint64_t _imm) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
{}
@@ -310,12 +310,12 @@
class RegMiscRegImmOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
ArmISA::MiscRegIndex op1;
uint64_t imm;
RegMiscRegImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
+ OpClass __opClass, RegIndex _dest,
ArmISA::MiscRegIndex _op1, uint64_t _imm) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
@@ -328,12 +328,12 @@
class RegImmImmOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
uint64_t imm1;
uint64_t imm2;
RegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
+ OpClass __opClass, RegIndex _dest,
uint64_t _imm1, uint64_t _imm2) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), imm1(_imm1), imm2(_imm2)
@@ -346,14 +346,14 @@
class RegRegImmImmOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
uint64_t imm1;
uint64_t imm2;
RegRegImmImmOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1, uint64_t _imm1, uint64_t _imm2) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm1, uint64_t _imm2) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
{}
@@ -365,15 +365,15 @@
class RegImmRegShiftOp : public ArmISA::PredOp
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
- ArmISA::IntRegIndex op1;
+ RegIndex op1;
int32_t shiftAmt;
ArmISA::ArmShiftType shiftType;
RegImmRegShiftOp(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- uint64_t _imm, ArmISA::IntRegIndex _op1,
+ OpClass __opClass, RegIndex _dest,
+ uint64_t _imm, RegIndex _op1,
int32_t _shiftAmt, ArmISA::ArmShiftType _shiftType) :
ArmISA::PredOp(mnem, _machInst, __opClass),
dest(_dest), imm(_imm), op1(_op1),
@@ -444,7 +444,7 @@
protected:
TlbiOp(const char *mnem, ArmISA::ExtMachInst _machInst,
OpClass __opClass, ArmISA::MiscRegIndex _dest,
- ArmISA::IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _op1, uint64_t _imm) :
MiscRegRegImmOp(mnem, _machInst, __opClass, _dest, _op1, _imm)
{}
diff --git a/src/arch/arm/insts/misc64.hh b/src/arch/arm/insts/misc64.hh
index 6241c43..5e166f5 100644
--- a/src/arch/arm/insts/misc64.hh
+++ b/src/arch/arm/insts/misc64.hh
@@ -60,14 +60,14 @@
class RegRegImmImmOp64 : public ArmISA::ArmStaticInst
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
uint64_t imm1;
uint64_t imm2;
RegRegImmImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1, uint64_t _imm1,
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm1,
int64_t _imm2) :
ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm1(_imm1), imm2(_imm2)
@@ -80,14 +80,14 @@
class RegRegRegImmOp64 : public ArmISA::ArmStaticInst
{
protected:
- ArmISA::IntRegIndex dest;
- ArmISA::IntRegIndex op1;
- ArmISA::IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
uint64_t imm;
RegRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
- ArmISA::IntRegIndex _op1, ArmISA::IntRegIndex _op2,
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), imm(_imm)
@@ -177,12 +177,12 @@
{
protected:
ArmISA::MiscRegIndex dest;
- ArmISA::IntRegIndex op1;
+ RegIndex op1;
uint32_t imm;
MiscRegRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
OpClass __opClass, ArmISA::MiscRegIndex _dest,
- ArmISA::IntRegIndex _op1, uint32_t _imm) :
+ RegIndex _op1, uint32_t _imm) :
MiscRegOp64(mnem, _machInst, __opClass, false),
dest(_dest), op1(_op1), imm(_imm)
{}
@@ -194,12 +194,12 @@
class RegMiscRegImmOp64 : public MiscRegOp64
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
ArmISA::MiscRegIndex op1;
uint32_t imm;
RegMiscRegImmOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest,
+ OpClass __opClass, RegIndex _dest,
ArmISA::MiscRegIndex _op1, uint32_t _imm) :
MiscRegOp64(mnem, _machInst, __opClass, true),
dest(_dest), op1(_op1), imm(_imm)
@@ -240,10 +240,10 @@
class RegNone : public ArmISA::ArmStaticInst
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
RegNone(const char *mnem, ArmISA::ExtMachInst _machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest) :
+ OpClass __opClass, RegIndex _dest) :
ArmISA::ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest)
{}
@@ -257,7 +257,7 @@
protected:
TlbiOp64(const char *mnem, ArmISA::ExtMachInst _machInst,
OpClass __opClass, ArmISA::MiscRegIndex _dest,
- ArmISA::IntRegIndex _op1, uint32_t _imm) :
+ RegIndex _op1, uint32_t _imm) :
MiscRegRegImmOp64(mnem, _machInst, __opClass, _dest, _op1, _imm)
{}
diff --git a/src/arch/arm/insts/mult.hh b/src/arch/arm/insts/mult.hh
index 5939b56..11c2d96 100644
--- a/src/arch/arm/insts/mult.hh
+++ b/src/arch/arm/insts/mult.hh
@@ -53,10 +53,10 @@
class Mult3 : public PredOp
{
protected:
- IntRegIndex reg0, reg1, reg2;
+ RegIndex reg0, reg1, reg2;
Mult3(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _reg0, IntRegIndex _reg1, IntRegIndex _reg2) :
+ RegIndex _reg0, RegIndex _reg1, RegIndex _reg2) :
PredOp(mnem, _machInst, __opClass),
reg0(_reg0), reg1(_reg1), reg2(_reg2)
{}
@@ -68,11 +68,11 @@
class Mult4 : public Mult3
{
protected:
- IntRegIndex reg3;
+ RegIndex reg3;
Mult4(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _reg0, IntRegIndex _reg1,
- IntRegIndex _reg2, IntRegIndex _reg3) :
+ RegIndex _reg0, RegIndex _reg1,
+ RegIndex _reg2, RegIndex _reg3) :
Mult3(mnem, _machInst, __opClass, _reg0, _reg1, _reg2), reg3(_reg3)
{}
};
diff --git a/src/arch/arm/insts/pred_inst.cc b/src/arch/arm/insts/pred_inst.cc
index 517d511..c5fee01 100644
--- a/src/arch/arm/insts/pred_inst.cc
+++ b/src/arch/arm/insts/pred_inst.cc
@@ -54,10 +54,7 @@
uint32_t imm = machInst.imm;
imm = (imm << (32 - rotate)) | (imm >> rotate);
printDataInst(ss, false, machInst.opcode4 == 0, machInst.sField,
- (IntRegIndex)(uint32_t)machInst.rd,
- (IntRegIndex)(uint32_t)machInst.rn,
- (IntRegIndex)(uint32_t)machInst.rm,
- (IntRegIndex)(uint32_t)machInst.rs,
+ machInst.rd, machInst.rn, machInst.rm, machInst.rs,
machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
imm);
return ss.str();
@@ -69,10 +66,7 @@
{
std::stringstream ss;
printDataInst(ss, true, machInst.opcode4 == 0, machInst.sField,
- (IntRegIndex)(uint32_t)machInst.rd,
- (IntRegIndex)(uint32_t)machInst.rn,
- (IntRegIndex)(uint32_t)machInst.rm,
- (IntRegIndex)(uint32_t)machInst.rs,
+ machInst.rd, machInst.rn, machInst.rm, machInst.rs,
machInst.shiftSize, (ArmShiftType)(uint32_t)machInst.shift,
imm);
return ss.str();
@@ -84,7 +78,7 @@
{
std::stringstream ss;
printDataInst(ss, true, false, /*XXX not really s*/ false, dest, op1,
- INTREG_ZERO, INTREG_ZERO, 0, LSL, imm);
+ int_reg::Zero, int_reg::Zero, 0, LSL, imm);
return ss.str();
}
@@ -94,7 +88,7 @@
{
std::stringstream ss;
printDataInst(ss, false, true, /*XXX not really s*/ false, dest, op1,
- op2, INTREG_ZERO, shiftAmt, shiftType, 0);
+ op2, int_reg::Zero, shiftAmt, shiftType, 0);
return ss.str();
}
diff --git a/src/arch/arm/insts/pred_inst.hh b/src/arch/arm/insts/pred_inst.hh
index a4a6567..29581a9 100644
--- a/src/arch/arm/insts/pred_inst.hh
+++ b/src/arch/arm/insts/pred_inst.hh
@@ -283,14 +283,14 @@
class DataImmOp : public PredOp
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
uint32_t imm;
// Whether the carry flag should be modified if that's an option for
// this instruction.
bool rotC;
DataImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, uint32_t _imm, bool _rotC) :
+ RegIndex _dest, RegIndex _op1, uint32_t _imm, bool _rotC) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm), rotC(_rotC)
{}
@@ -302,12 +302,12 @@
class DataRegOp : public PredOp
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
int32_t shiftAmt;
ArmShiftType shiftType;
DataRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2),
@@ -321,12 +321,12 @@
class DataRegRegOp : public PredOp
{
protected:
- IntRegIndex dest, op1, op2, shift;
+ RegIndex dest, op1, op2, shift;
ArmShiftType shiftType;
DataRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _shift, ArmShiftType _shiftType) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _shift, ArmShiftType _shiftType) :
PredOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), shift(_shift),
shiftType(_shiftType)
diff --git a/src/arch/arm/insts/static_inst.cc b/src/arch/arm/insts/static_inst.cc
index 4541240..c7b2e44 100644
--- a/src/arch/arm/insts/static_inst.cc
+++ b/src/arch/arm/insts/static_inst.cc
@@ -302,17 +302,17 @@
if (opWidth == 0)
opWidth = intWidth;
if (aarch64) {
- if (reg_idx == INTREG_UREG0)
+ if (reg_idx == int_reg::Ureg0)
ccprintf(os, "ureg0");
- else if (reg_idx == INTREG_SPX)
+ else if (reg_idx == int_reg::Spx)
ccprintf(os, "%s%s", (opWidth == 32) ? "w" : "", "sp");
- else if (reg_idx == INTREG_X31)
+ else if (reg_idx == int_reg::X31)
ccprintf(os, "%szr", (opWidth == 32) ? "w" : "x");
else
ccprintf(os, "%s%d", (opWidth == 32) ? "w" : "x", reg_idx);
} else {
switch (reg_idx) {
- case PCReg:
+ case int_reg::Pc:
ccprintf(os, "pc");
break;
case StackPointerReg:
@@ -496,15 +496,15 @@
void
ArmStaticInst::printShiftOperand(std::ostream &os,
- IntRegIndex rm,
+ RegIndex rm,
bool immShift,
uint32_t shiftAmt,
- IntRegIndex rs,
+ RegIndex rs,
ArmShiftType type) const
{
bool firstOp = false;
- if (rm != INTREG_ZERO) {
+ if (rm != int_reg::Zero) {
printIntReg(os, rm);
}
@@ -560,7 +560,7 @@
void
ArmStaticInst::printExtendOperand(bool firstOperand, std::ostream &os,
- IntRegIndex rm, ArmExtendType type,
+ RegIndex rm, ArmExtendType type,
int64_t shiftAmt) const
{
if (!firstOperand)
@@ -592,21 +592,21 @@
void
ArmStaticInst::printDataInst(std::ostream &os, bool withImm,
- bool immShift, bool s, IntRegIndex rd, IntRegIndex rn,
- IntRegIndex rm, IntRegIndex rs, uint32_t shiftAmt,
+ bool immShift, bool s, RegIndex rd, RegIndex rn,
+ RegIndex rm, RegIndex rs, uint32_t shiftAmt,
ArmShiftType type, uint64_t imm) const
{
printMnemonic(os, s ? "s" : "");
bool firstOp = true;
// Destination
- if (rd != INTREG_ZERO) {
+ if (rd != int_reg::Zero) {
firstOp = false;
printIntReg(os, rd);
}
// Source 1.
- if (rn != INTREG_ZERO) {
+ if (rn != int_reg::Zero) {
if (!firstOp)
os << ", ";
firstOp = false;
diff --git a/src/arch/arm/insts/static_inst.hh b/src/arch/arm/insts/static_inst.hh
index 290ff3c..e30ba28 100644
--- a/src/arch/arm/insts/static_inst.hh
+++ b/src/arch/arm/insts/static_inst.hh
@@ -184,18 +184,18 @@
void printMemSymbol(std::ostream &os, const loader::SymbolTable *symtab,
const std::string &prefix, const Addr addr,
const std::string &suffix) const;
- void printShiftOperand(std::ostream &os, IntRegIndex rm,
+ void printShiftOperand(std::ostream &os, RegIndex rm,
bool immShift, uint32_t shiftAmt,
- IntRegIndex rs, ArmShiftType type) const;
+ RegIndex rs, ArmShiftType type) const;
void printExtendOperand(bool firstOperand, std::ostream &os,
- IntRegIndex rm, ArmExtendType type,
+ RegIndex rm, ArmExtendType type,
int64_t shiftAmt) const;
void printPFflags(std::ostream &os, int flag) const;
void printDataInst(std::ostream &os, bool withImm) const;
void printDataInst(std::ostream &os, bool withImm, bool immShift, bool s,
- IntRegIndex rd, IntRegIndex rn, IntRegIndex rm,
- IntRegIndex rs, uint32_t shiftAmt, ArmShiftType type,
+ RegIndex rd, RegIndex rn, RegIndex rm,
+ RegIndex rs, uint32_t shiftAmt, ArmShiftType type,
uint64_t imm) const;
void
diff --git a/src/arch/arm/insts/sve.hh b/src/arch/arm/insts/sve.hh
index 5a0f605..f9939e1 100644
--- a/src/arch/arm/insts/sve.hh
+++ b/src/arch/arm/insts/sve.hh
@@ -60,12 +60,12 @@
class SveIndexIIOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
int8_t imm1;
int8_t imm2;
SveIndexIIOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
+ OpClass __opClass, RegIndex _dest,
int8_t _imm1, int8_t _imm2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), imm1(_imm1), imm2(_imm2)
@@ -77,13 +77,13 @@
class SveIndexIROp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
int8_t imm1;
- IntRegIndex op2;
+ RegIndex op2;
SveIndexIROp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- int8_t _imm1, IntRegIndex _op2) :
+ OpClass __opClass, RegIndex _dest,
+ int8_t _imm1, RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), imm1(_imm1), op2(_op2)
{}
@@ -94,13 +94,13 @@
class SveIndexRIOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
int8_t imm2;
SveIndexRIOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _op1, int8_t _imm2) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, int8_t _imm2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm2(_imm2)
{}
@@ -111,13 +111,13 @@
class SveIndexRROp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
SveIndexRROp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
@@ -129,13 +129,13 @@
class SvePredCountOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
+ RegIndex dest;
+ RegIndex gp;
bool srcIs32b;
bool destIsVec;
SvePredCountOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp,
+ OpClass __opClass, RegIndex _dest, RegIndex _gp,
bool _srcIs32b = false, bool _destIsVec = false) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp),
@@ -149,13 +149,13 @@
class SvePredCountPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex gp;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex gp;
SvePredCountPredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _gp) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), gp(_gp)
{}
@@ -167,11 +167,11 @@
class SveWhileOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
bool srcIs32b;
SveWhileOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
bool _srcIs32b) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), srcIs32b(_srcIs32b)
@@ -184,10 +184,10 @@
class SveCompTermOp : public ArmStaticInst
{
protected:
- IntRegIndex op1, op2;
+ RegIndex op1, op2;
SveCompTermOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _op1, RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
op1(_op1), op2(_op2)
{}
@@ -199,10 +199,10 @@
class SveUnaryPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, gp;
+ RegIndex dest, op1, gp;
SveUnaryPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), gp(_gp)
{}
@@ -215,10 +215,10 @@
class SveUnaryUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
SveUnaryUnpredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1)
{}
@@ -231,11 +231,11 @@
class SveUnaryWideImmUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
SveUnaryWideImmUnpredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
+ OpClass __opClass, RegIndex _dest,
uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), imm(_imm)
@@ -249,15 +249,15 @@
class SveUnaryWideImmPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
- IntRegIndex gp;
+ RegIndex gp;
bool isMerging;
SveUnaryWideImmPredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- uint64_t _imm, IntRegIndex _gp, bool _isMerging) :
+ OpClass __opClass, RegIndex _dest,
+ uint64_t _imm, RegIndex _gp, bool _isMerging) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), imm(_imm), gp(_gp), isMerging(_isMerging)
{}
@@ -270,11 +270,11 @@
class SveBinImmUnpredConstrOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
uint64_t imm;
SveBinImmUnpredConstrOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
@@ -288,11 +288,11 @@
class SveBinImmPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, gp;
+ RegIndex dest, gp;
uint64_t imm;
SveBinImmPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp) :
+ RegIndex _dest, uint64_t _imm, RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), imm(_imm)
{}
@@ -305,11 +305,11 @@
class SveBinWideImmUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
SveBinWideImmUnpredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
+ OpClass __opClass, RegIndex _dest,
uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), imm(_imm)
@@ -323,11 +323,11 @@
class SveBinDestrPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op2, gp;
+ RegIndex dest, op2, gp;
SveBinDestrPredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2,
- IntRegIndex _gp) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op2,
+ RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op2(_op2), gp(_gp)
{}
@@ -340,12 +340,12 @@
class SveBinConstrPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2, gp;
+ RegIndex dest, op1, op2, gp;
SvePredType predType;
SveBinConstrPredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, IntRegIndex _gp,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, RegIndex _gp,
SvePredType _predType) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), gp(_gp), predType(_predType)
@@ -359,10 +359,10 @@
class SveBinUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
SveBinUnpredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
@@ -375,12 +375,12 @@
class SveBinIdxUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
uint8_t index;
SveBinIdxUnpredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, uint8_t _index) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, uint8_t _index) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), index(_index)
{}
@@ -393,12 +393,12 @@
class SvePredLogicalOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2, gp;
+ RegIndex dest, op1, op2, gp;
bool isSel;
SvePredLogicalOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, IntRegIndex _gp, bool _isSel = false) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, RegIndex _gp, bool _isSel = false) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), gp(_gp), isSel(_isSel)
{}
@@ -411,11 +411,11 @@
class SvePredBinPermOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
SvePredBinPermOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
@@ -428,11 +428,11 @@
class SveCmpOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, gp, op1, op2;
+ RegIndex dest, gp, op1, op2;
SveCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), op1(_op1), op2(_op2)
{}
@@ -445,12 +445,12 @@
class SveCmpImmOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, gp, op1;
+ RegIndex dest, gp, op1;
uint64_t imm;
SveCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm,
- IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, uint64_t _imm,
+ RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), op1(_op1), imm(_imm)
{}
@@ -463,11 +463,11 @@
class SveTerPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2, gp;
+ RegIndex dest, op1, op2, gp;
SveTerPredOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), gp(_gp)
{}
@@ -480,11 +480,11 @@
class SveTerImmUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op2;
+ RegIndex dest, op2;
uint64_t imm;
SveTerImmUnpredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op2,
+ OpClass __opClass, RegIndex _dest, RegIndex _op2,
uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op2(_op2), imm(_imm)
@@ -498,10 +498,10 @@
class SveReducOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, gp;
+ RegIndex dest, op1, gp;
SveReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), gp(_gp)
{}
@@ -514,10 +514,10 @@
class SveOrdReducOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, gp;
+ RegIndex dest, op1, gp;
SveOrdReducOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), gp(_gp)
{}
@@ -530,11 +530,11 @@
class SvePtrueOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
uint8_t imm;
SvePtrueOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, uint8_t _imm) :
+ OpClass __opClass, RegIndex _dest, uint8_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), imm(_imm)
{}
@@ -547,14 +547,14 @@
class SveIntCmpOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1, op2;
- IntRegIndex gp;
+ RegIndex dest;
+ RegIndex op1, op2;
+ RegIndex gp;
bool op2IsWide;
SveIntCmpOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _gp, bool _op2IsWide = false) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _gp, bool _op2IsWide = false) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), gp(_gp), op2IsWide(_op2IsWide)
{}
@@ -566,14 +566,14 @@
class SveIntCmpImmOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
int64_t imm;
- IntRegIndex gp;
+ RegIndex gp;
SveIntCmpImmOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, int64_t _imm,
- IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, int64_t _imm,
+ RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm), gp(_gp)
{}
@@ -593,13 +593,13 @@
};
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
uint8_t mult;
SveAdrOffsetFormat offsetFormat;
SveAdrOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, uint8_t _mult,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, uint8_t _mult,
SveAdrOffsetFormat _offsetFormat) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), mult(_mult),
@@ -613,7 +613,7 @@
class SveElemCountOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
uint8_t pattern;
uint8_t imm;
bool dstIsVec;
@@ -621,7 +621,7 @@
uint8_t esize;
SveElemCountOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, uint8_t _pattern, uint8_t _imm,
+ RegIndex _dest, uint8_t _pattern, uint8_t _imm,
bool _dstIsVec, bool _dstIs32b) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), pattern(_pattern), imm(_imm), dstIsVec(_dstIsVec),
@@ -635,13 +635,13 @@
class SvePartBrkOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex op1;
bool isMerging;
SvePartBrkOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _gp, RegIndex _op1,
bool _isMerging) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), op1(_op1), isMerging(_isMerging)
@@ -654,14 +654,14 @@
class SvePartBrkPropOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex op2;
- IntRegIndex gp;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
+ RegIndex gp;
SvePartBrkPropOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), gp(_gp)
{}
@@ -673,17 +673,17 @@
class SveSelectOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex gp;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex gp;
bool conditional;
bool scalar;
bool simdFp;
size_t scalar_width;
SveSelectOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _gp,
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _gp,
bool _conditional, bool _scalar,
bool _simdFp) :
ArmStaticInst(mnem, _machInst, __opClass),
@@ -698,13 +698,13 @@
class SveUnaryPredPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex gp;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex gp;
SveUnaryPredPredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _gp) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), gp(_gp)
{}
@@ -716,12 +716,12 @@
class SveTblOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
SveTblOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
@@ -733,11 +733,11 @@
class SveUnpackOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
SveUnpackOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1) :
+ RegIndex _dest, RegIndex _op1) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1)
{}
@@ -749,11 +749,11 @@
class SvePredTestOp : public ArmStaticInst
{
protected:
- IntRegIndex op1;
- IntRegIndex gp;
+ RegIndex op1;
+ RegIndex gp;
SvePredTestOp(const char* mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _op1, IntRegIndex _gp) :
+ RegIndex _op1, RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
op1(_op1), gp(_gp)
{}
@@ -765,10 +765,10 @@
class SvePredUnaryWImplicitSrcOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
SvePredUnaryWImplicitSrcOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest) :
+ OpClass __opClass, RegIndex _dest) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest)
{}
@@ -780,12 +780,12 @@
class SvePredUnaryWImplicitSrcPredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
+ RegIndex dest;
+ RegIndex gp;
SvePredUnaryWImplicitSrcPredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _gp) :
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _gp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp)
{}
@@ -797,10 +797,10 @@
class SvePredUnaryWImplicitDstOp : public ArmStaticInst
{
protected:
- IntRegIndex op1;
+ RegIndex op1;
SvePredUnaryWImplicitDstOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _op1) :
+ OpClass __opClass, RegIndex _op1) :
ArmStaticInst(mnem, _machInst, __opClass),
op1(_op1)
{}
@@ -824,12 +824,12 @@
class SveBinImmUnpredDestrOp : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
uint64_t imm;
SveBinImmUnpredDestrOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
@@ -842,11 +842,11 @@
class SveBinImmIdxUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
uint64_t imm;
SveBinImmIdxUnpredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), imm(_imm)
@@ -860,11 +860,11 @@
class SveUnarySca2VecUnpredOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1;
+ RegIndex dest, op1;
bool simdFp;
SveUnarySca2VecUnpredOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
bool _simdFp) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), simdFp(_simdFp)
@@ -878,14 +878,14 @@
class SveDotProdIdxOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
uint64_t imm;
uint8_t esize;
public:
SveDotProdIdxOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, uint64_t _imm) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, uint64_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), imm(_imm)
{}
@@ -898,13 +898,13 @@
class SveDotProdOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
uint8_t esize;
public:
SveDotProdOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2)
{}
@@ -917,13 +917,13 @@
class SveComplexOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2, gp;
+ RegIndex dest, op1, op2, gp;
uint8_t rot;
public:
SveComplexOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, IntRegIndex _gp, uint8_t _rot) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, RegIndex _gp, uint8_t _rot) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), gp(_gp), rot(_rot)
{}
@@ -936,13 +936,13 @@
class SveComplexIdxOp : public ArmStaticInst
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
uint8_t rot, imm;
public:
SveComplexIdxOp(const char* mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, uint8_t _rot, uint8_t _imm) :
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, uint8_t _rot, uint8_t _imm) :
ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), rot(_rot), imm(_imm)
{}
diff --git a/src/arch/arm/insts/sve_macromem.hh b/src/arch/arm/insts/sve_macromem.hh
index 84e2f94..8e94fa4 100644
--- a/src/arch/arm/insts/sve_macromem.hh
+++ b/src/arch/arm/insts/sve_macromem.hh
@@ -52,16 +52,16 @@
class SveLdStructSS : public PredMacroOp
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
- IntRegIndex offset;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
+ RegIndex offset;
uint8_t numregs;
public:
SveLdStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
- IntRegIndex _offset, uint8_t _numregs)
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
+ RegIndex _offset, uint8_t _numregs)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numregs)
{
@@ -71,12 +71,12 @@
for (int i = 0; i < numregs; ++i) {
microOps[i] = new MicroopLdMemType<Element>(
- mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
+ mnem, machInst, static_cast<RegIndex>(INTRLVREG0 + i),
_gp, _base, _offset, _numregs, i);
}
for (int i = 0; i < numregs; ++i) {
microOps[i + numregs] = new MicroopDeIntrlvType<Element>(
- mnem, machInst, static_cast<IntRegIndex>((_dest + i) % 32),
+ mnem, machInst, static_cast<RegIndex>((_dest + i) % 32),
_numregs, i, this);
}
@@ -124,16 +124,16 @@
class SveStStructSS : public PredMacroOp
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
- IntRegIndex offset;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
+ RegIndex offset;
uint8_t numregs;
public:
SveStStructSS(const char* mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
- IntRegIndex _offset, uint8_t _numregs)
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
+ RegIndex _offset, uint8_t _numregs)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), offset(_offset), numregs(_numregs)
{
@@ -143,13 +143,13 @@
for (int i = 0; i < numregs; ++i) {
microOps[i] = new MicroopIntrlvType<Element>(
- mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
+ mnem, machInst, static_cast<RegIndex>(INTRLVREG0 + i),
_dest, _numregs, i, this);
}
for (int i = 0; i < numregs; ++i) {
microOps[i + numregs] = new MicroopStMemType<Element>(
- mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
+ mnem, machInst, static_cast<RegIndex>(INTRLVREG0 + i),
_gp, _base, _offset, _numregs, i);
}
@@ -198,15 +198,15 @@
class SveLdStructSI : public PredMacroOp
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
int64_t imm;
uint8_t numregs;
public:
SveLdStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
int64_t _imm, uint8_t _numregs)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), imm(_imm), numregs(_numregs)
@@ -217,12 +217,12 @@
for (int i = 0; i < numregs; ++i) {
microOps[i] = new MicroopLdMemType<Element>(
- mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
+ mnem, machInst, static_cast<RegIndex>(INTRLVREG0 + i),
_gp, _base, _imm, _numregs, i);
}
for (int i = 0; i < numregs; ++i) {
microOps[i + numregs] = new MicroopDeIntrlvType<Element>(
- mnem, machInst, static_cast<IntRegIndex>((_dest + i) % 32),
+ mnem, machInst, static_cast<RegIndex>((_dest + i) % 32),
_numregs, i, this);
}
@@ -271,15 +271,15 @@
class SveStStructSI : public PredMacroOp
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
int64_t imm;
uint8_t numregs;
public:
SveStStructSI(const char* mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
int64_t _imm, uint8_t _numregs)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), imm(_imm), numregs(_numregs)
@@ -290,13 +290,13 @@
for (int i = 0; i < numregs; ++i) {
microOps[i] = new MicroopIntrlvType<Element>(
- mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
+ mnem, machInst, static_cast<RegIndex>(INTRLVREG0 + i),
_dest, _numregs, i, this);
}
for (int i = 0; i < numregs; ++i) {
microOps[i + numregs] = new MicroopStMemType<Element>(
- mnem, machInst, static_cast<IntRegIndex>(INTRLVREG0 + i),
+ mnem, machInst, static_cast<RegIndex>(INTRLVREG0 + i),
_gp, _base, _imm, _numregs, i);
}
@@ -345,14 +345,14 @@
class SveIndexedMemVI : public PredMacroOp
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
uint64_t imm;
public:
SveIndexedMemVI(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
uint64_t _imm, bool firstFault)
: PredMacroOp(mnem, machInst, __opClass),
dest(_dest), gp(_gp), base(_base), imm(_imm)
@@ -389,7 +389,7 @@
for (int i = 0; i < num_elems; i++, uop++) {
*uop = new MicroopType<RegElemType, MemElemType>(
mnem, machInst, __opClass, _dest, _gp,
- isLoad ? (IntRegIndex) VECREG_UREG0 : _base, _imm, i,
+ isLoad ? (RegIndex) VECREG_UREG0 : _base, _imm, i,
num_elems, firstFault);
}
@@ -442,10 +442,10 @@
class SveIndexedMemSV : public PredMacroOp
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
- IntRegIndex offset;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
+ RegIndex offset;
bool offsetIs32;
bool offsetIsSigned;
@@ -453,8 +453,8 @@
public:
SveIndexedMemSV(const char *mnem, ExtMachInst machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
- IntRegIndex _offset, bool _offsetIs32,
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
+ RegIndex _offset, bool _offsetIs32,
bool _offsetIsSigned, bool _offsetIsScaled,
bool firstFault)
: PredMacroOp(mnem, machInst, __opClass),
@@ -494,7 +494,7 @@
for (int i = 0; i < num_elems; i++, uop++) {
*uop = new MicroopType<RegElemType, MemElemType>(
mnem, machInst, __opClass, _dest, _gp, _base,
- isLoad ? (IntRegIndex) VECREG_UREG0 : _offset, _offsetIs32,
+ isLoad ? (RegIndex) VECREG_UREG0 : _offset, _offsetIs32,
_offsetIsSigned, _offsetIsScaled, i, num_elems, firstFault);
}
diff --git a/src/arch/arm/insts/sve_mem.hh b/src/arch/arm/insts/sve_mem.hh
index 167591c..6d94e0a 100644
--- a/src/arch/arm/insts/sve_mem.hh
+++ b/src/arch/arm/insts/sve_mem.hh
@@ -50,8 +50,8 @@
class SveMemVecFillSpill : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex base;
uint64_t imm;
/// True if the base register is SP (used for SP alignment checking).
@@ -60,8 +60,8 @@
unsigned memAccessFlags;
SveMemVecFillSpill(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _base, uint64_t _imm)
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _base, uint64_t _imm)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), base(_base), imm(_imm),
memAccessFlags(ArmISA::MMU::AllowUnaligned)
@@ -76,8 +76,8 @@
class SveMemPredFillSpill : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex base;
uint64_t imm;
/// True if the base register is SP (used for SP alignment checking).
@@ -86,8 +86,8 @@
unsigned memAccessFlags;
SveMemPredFillSpill(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _base, uint64_t _imm)
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _base, uint64_t _imm)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), base(_base), imm(_imm),
memAccessFlags(ArmISA::MMU::AllowUnaligned)
@@ -102,10 +102,10 @@
class SveContigMemSS : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
- IntRegIndex offset;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
+ RegIndex offset;
/// True if the base register is SP (used for SP alignment checking).
bool baseIsSP;
@@ -113,8 +113,8 @@
unsigned memAccessFlags;
SveContigMemSS(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
- IntRegIndex _offset)
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
+ RegIndex _offset)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), base(_base), offset(_offset),
memAccessFlags(ArmISA::MMU::AllowUnaligned)
@@ -129,9 +129,9 @@
class SveContigMemSI : public ArmStaticInst
{
protected:
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
uint64_t imm;
/// True if the base register is SP (used for SP alignment checking).
@@ -140,7 +140,7 @@
unsigned memAccessFlags;
SveContigMemSI(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
uint64_t _imm)
: ArmStaticInst(mnem, _machInst, __opClass),
dest(_dest), gp(_gp), base(_base), imm(_imm),
diff --git a/src/arch/arm/insts/tme64.cc b/src/arch/arm/insts/tme64.cc
index 7a6ede7..2b82283 100644
--- a/src/arch/arm/insts/tme64.cc
+++ b/src/arch/arm/insts/tme64.cc
@@ -112,7 +112,7 @@
return NoFault;
}
-Tstart64::Tstart64(ExtMachInst machInst, IntRegIndex _dest)
+Tstart64::Tstart64(ExtMachInst machInst, RegIndex _dest)
: TmeRegNone64("tstart", machInst, MemReadOp, _dest)
{
setRegIdxArrays(
@@ -141,7 +141,7 @@
return NoFault;
}
-Ttest64::Ttest64(ExtMachInst machInst, IntRegIndex _dest)
+Ttest64::Ttest64(ExtMachInst machInst, RegIndex _dest)
: TmeRegNone64("ttest", machInst, MemReadOp, _dest)
{
setRegIdxArrays(
diff --git a/src/arch/arm/insts/tme64.hh b/src/arch/arm/insts/tme64.hh
index c61764a..c8994f3 100644
--- a/src/arch/arm/insts/tme64.hh
+++ b/src/arch/arm/insts/tme64.hh
@@ -86,10 +86,10 @@
class TmeRegNone64 : public ArmISA::ArmStaticInst
{
protected:
- ArmISA::IntRegIndex dest;
+ RegIndex dest;
TmeRegNone64(const char *mnem, ArmISA::ExtMachInst machInst,
- OpClass __opClass, ArmISA::IntRegIndex _dest)
+ OpClass __opClass, RegIndex _dest)
: ArmISA::ArmStaticInst(mnem, machInst, __opClass),
dest(_dest)
{}
@@ -104,7 +104,7 @@
RegId destRegIdxArr[1];
public:
- Tstart64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
+ Tstart64(ArmISA::ExtMachInst, RegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const;
@@ -117,7 +117,7 @@
RegId destRegIdxArr[1];
public:
- Ttest64(ArmISA::ExtMachInst, ArmISA::IntRegIndex);
+ Ttest64(ArmISA::ExtMachInst, RegIndex);
Fault execute(ExecContext *, Trace::InstRecord *) const;
};
diff --git a/src/arch/arm/insts/tme64ruby.cc b/src/arch/arm/insts/tme64ruby.cc
index b35433a..6999924 100644
--- a/src/arch/arm/insts/tme64ruby.cc
+++ b/src/arch/arm/insts/tme64ruby.cc
@@ -122,7 +122,7 @@
tc->getIsaPtr()->globalClearExclusive();
}
- xc->setRegOperand(this, 0, (Dest64) & mask(intWidth));
+ xc->setRegOperand(this, 0, Dest64 & mask(intWidth));
uint64_t final_val = Dest64;
@@ -155,7 +155,7 @@
if (fault == NoFault) {
uint64_t final_val = Dest64;
- xc->setRegOperand(this, 0, (Dest64) & mask(intWidth));
+ xc->setRegOperand(this, 0, Dest64 & mask(intWidth));
if (traceData) { traceData->setData(final_val); }
}
diff --git a/src/arch/arm/insts/vfp.cc b/src/arch/arm/insts/vfp.cc
index 4246af6..a76fd1d 100644
--- a/src/arch/arm/insts/vfp.cc
+++ b/src/arch/arm/insts/vfp.cc
@@ -1163,21 +1163,21 @@
double FpOp::unaryOp(FPSCR &fpscr, double op1, double (*func)(double),
bool flush, uint32_t rMode) const;
-IntRegIndex
-VfpMacroOp::addStride(IntRegIndex idx, unsigned stride)
+RegIndex
+VfpMacroOp::addStride(RegIndex idx, unsigned stride)
{
if (wide) {
stride *= 2;
}
unsigned offset = idx % 8;
- idx = (IntRegIndex)(idx - offset);
+ idx = (RegIndex)(idx - offset);
offset += stride;
- idx = (IntRegIndex)(idx + (offset % 8));
+ idx = (RegIndex)(idx + (offset % 8));
return idx;
}
void
-VfpMacroOp::nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2)
+VfpMacroOp::nextIdxs(RegIndex &dest, RegIndex &op1, RegIndex &op2)
{
unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
assert(!inScalarBank(dest));
@@ -1189,7 +1189,7 @@
}
void
-VfpMacroOp::nextIdxs(IntRegIndex &dest, IntRegIndex &op1)
+VfpMacroOp::nextIdxs(RegIndex &dest, RegIndex &op1)
{
unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
assert(!inScalarBank(dest));
@@ -1200,7 +1200,7 @@
}
void
-VfpMacroOp::nextIdxs(IntRegIndex &dest)
+VfpMacroOp::nextIdxs(RegIndex &dest)
{
unsigned stride = (machInst.fpscrStride == 0) ? 1 : 2;
assert(!inScalarBank(dest));
diff --git a/src/arch/arm/insts/vfp.hh b/src/arch/arm/insts/vfp.hh
index e2409ac..96db063 100644
--- a/src/arch/arm/insts/vfp.hh
+++ b/src/arch/arm/insts/vfp.hh
@@ -458,7 +458,7 @@
{
public:
static bool
- inScalarBank(IntRegIndex idx)
+ inScalarBank(RegIndex idx)
{
return (idx % 32) < 8;
}
@@ -471,10 +471,10 @@
PredMacroOp(mnem, _machInst, __opClass), wide(_wide)
{}
- IntRegIndex addStride(IntRegIndex idx, unsigned stride);
- void nextIdxs(IntRegIndex &dest, IntRegIndex &op1, IntRegIndex &op2);
- void nextIdxs(IntRegIndex &dest, IntRegIndex &op1);
- void nextIdxs(IntRegIndex &dest);
+ RegIndex addStride(RegIndex idx, unsigned stride);
+ void nextIdxs(RegIndex &dest, RegIndex &op1, RegIndex &op2);
+ void nextIdxs(RegIndex &dest, RegIndex &op1);
+ void nextIdxs(RegIndex &dest);
};
template <typename T>
@@ -901,12 +901,12 @@
class FpCondCompRegOp : public FpOp
{
protected:
- IntRegIndex op1, op2;
+ RegIndex op1, op2;
ConditionCode condCode;
uint8_t defCc;
FpCondCompRegOp(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _op1, IntRegIndex _op2,
+ OpClass __opClass, RegIndex _op1, RegIndex _op2,
ConditionCode _condCode, uint8_t _defCc) :
FpOp(mnem, _machInst, __opClass),
op1(_op1), op2(_op2), condCode(_condCode), defCc(_defCc)
@@ -919,11 +919,11 @@
class FpCondSelOp : public FpOp
{
protected:
- IntRegIndex dest, op1, op2;
+ RegIndex dest, op1, op2;
ConditionCode condCode;
FpCondSelOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
ConditionCode _condCode) :
FpOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), condCode(_condCode)
@@ -936,11 +936,11 @@
class FpRegRegOp : public FpOp
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
FpRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
VfpMicroMode mode = VfpNotAMicroop) :
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1)
{
@@ -954,11 +954,11 @@
class FpRegImmOp : public FpOp
{
protected:
- IntRegIndex dest;
+ RegIndex dest;
uint64_t imm;
FpRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, uint64_t _imm,
+ RegIndex _dest, uint64_t _imm,
VfpMicroMode mode = VfpNotAMicroop) :
FpOp(mnem, _machInst, __opClass), dest(_dest), imm(_imm)
{
@@ -972,12 +972,12 @@
class FpRegRegImmOp : public FpOp
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
uint64_t imm;
FpRegRegImmOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), imm(_imm)
{
@@ -991,12 +991,12 @@
class FpRegRegRegOp : public FpOp
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
FpRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
VfpMicroMode mode = VfpNotAMicroop) :
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2)
{
@@ -1010,14 +1010,14 @@
class FpRegRegRegCondOp : public FpOp
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
ConditionCode cond;
FpRegRegRegCondOp(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, ConditionCode _cond,
+ OpClass __opClass, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, ConditionCode _cond,
VfpMicroMode mode = VfpNotAMicroop) :
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2),
cond(_cond)
@@ -1032,14 +1032,14 @@
class FpRegRegRegRegOp : public FpOp
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex op2;
- IntRegIndex op3;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
+ RegIndex op3;
FpRegRegRegRegOp(const char *mnem, ExtMachInst _machInst, OpClass __opClass,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _op3, VfpMicroMode mode = VfpNotAMicroop) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _op3, VfpMicroMode mode = VfpNotAMicroop) :
FpOp(mnem, _machInst, __opClass), dest(_dest), op1(_op1), op2(_op2),
op3(_op3)
{
@@ -1053,14 +1053,14 @@
class FpRegRegRegImmOp : public FpOp
{
protected:
- IntRegIndex dest;
- IntRegIndex op1;
- IntRegIndex op2;
+ RegIndex dest;
+ RegIndex op1;
+ RegIndex op2;
uint64_t imm;
FpRegRegRegImmOp(const char *mnem, ExtMachInst _machInst,
- OpClass __opClass, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ OpClass __opClass, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop) :
FpOp(mnem, _machInst, __opClass),
dest(_dest), op1(_op1), op2(_op2), imm(_imm)
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index e1d5ab9..ad7320d 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -92,7 +92,7 @@
_decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
afterStartup(false)
{
- _regClasses.emplace_back(NUM_INTREGS, debug::IntRegs);
+ _regClasses.emplace_back(int_reg::NumRegs, debug::IntRegs);
_regClasses.emplace_back(0, debug::FloatRegs);
_regClasses.emplace_back(NumVecRegs, vecRegClassOps, debug::VecRegs,
sizeof(VecRegContainer));
@@ -563,8 +563,10 @@
void
ISA::copyRegsFrom(ThreadContext *src)
{
- for (int i = 0; i < NUM_INTREGS; i++)
- tc->setIntRegFlat(i, src->readIntRegFlat(i));
+ for (int i = 0; i < int_reg::NumRegs; i++) {
+ RegId reg(IntRegClass, i);
+ tc->setRegFlat(reg, src->getRegFlat(reg));
+ }
for (int i = 0; i < NUM_CCREGS; i++)
tc->setCCReg(i, src->readCCReg(i));
@@ -947,15 +949,15 @@
}
case MISCREG_SP_EL0:
{
- return tc->readIntReg(INTREG_SP0);
+ return tc->getReg(int_reg::Sp0);
}
case MISCREG_SP_EL1:
{
- return tc->readIntReg(INTREG_SP1);
+ return tc->getReg(int_reg::Sp1);
}
case MISCREG_SP_EL2:
{
- return tc->readIntReg(INTREG_SP2);
+ return tc->getReg(int_reg::Sp2);
}
case MISCREG_SPSEL:
{
@@ -1889,13 +1891,13 @@
}
break;
case MISCREG_SP_EL0:
- tc->setIntReg(INTREG_SP0, newVal);
+ tc->setReg(int_reg::Sp0, newVal);
break;
case MISCREG_SP_EL1:
- tc->setIntReg(INTREG_SP1, newVal);
+ tc->setReg(int_reg::Sp1, newVal);
break;
case MISCREG_SP_EL2:
- tc->setIntReg(INTREG_SP2, newVal);
+ tc->setReg(int_reg::Sp2, newVal);
break;
case MISCREG_SPSEL:
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 595e8df..599411f 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -567,39 +567,39 @@
void initializeMiscRegMetadata();
RegVal miscRegs[NUM_MISCREGS];
- const IntRegIndex *intRegMap;
+ const RegId *intRegMap;
void
updateRegMap(CPSR cpsr)
{
if (cpsr.width == 0) {
- intRegMap = IntReg64Map;
+ intRegMap = int_reg::Reg64Map;
} else {
switch (cpsr.mode) {
case MODE_USER:
case MODE_SYSTEM:
- intRegMap = IntRegUsrMap;
+ intRegMap = int_reg::RegUsrMap;
break;
case MODE_FIQ:
- intRegMap = IntRegFiqMap;
+ intRegMap = int_reg::RegFiqMap;
break;
case MODE_IRQ:
- intRegMap = IntRegIrqMap;
+ intRegMap = int_reg::RegIrqMap;
break;
case MODE_SVC:
- intRegMap = IntRegSvcMap;
+ intRegMap = int_reg::RegSvcMap;
break;
case MODE_MON:
- intRegMap = IntRegMonMap;
+ intRegMap = int_reg::RegMonMap;
break;
case MODE_ABORT:
- intRegMap = IntRegAbtMap;
+ intRegMap = int_reg::RegAbtMap;
break;
case MODE_HYP:
- intRegMap = IntRegHypMap;
+ intRegMap = int_reg::RegHypMap;
break;
case MODE_UNDEFINED:
- intRegMap = IntRegUndMap;
+ intRegMap = int_reg::RegUndMap;
break;
default:
panic("Unrecognized mode setting in CPSR.\n");
@@ -674,25 +674,25 @@
flattenIntIndex(int reg) const
{
assert(reg >= 0);
- if (reg < NUM_ARCH_INTREGS) {
+ if (reg < int_reg::NumArchRegs) {
return intRegMap[reg];
- } else if (reg < NUM_INTREGS) {
+ } else if (reg < int_reg::NumRegs) {
return reg;
- } else if (reg == INTREG_SPX) {
+ } else if (reg == int_reg::Spx) {
CPSR cpsr = miscRegs[MISCREG_CPSR];
ExceptionLevel el = opModeToEL(
(OperatingMode) (uint8_t) cpsr.mode);
if (!cpsr.sp && el != EL0)
- return INTREG_SP0;
+ return int_reg::Sp0;
switch (el) {
case EL3:
- return INTREG_SP3;
+ return int_reg::Sp3;
case EL2:
- return INTREG_SP2;
+ return int_reg::Sp2;
case EL1:
- return INTREG_SP1;
+ return int_reg::Sp1;
case EL0:
- return INTREG_SP0;
+ return int_reg::Sp0;
default:
panic("Invalid exception level");
return 0; // Never happens.
diff --git a/src/arch/arm/isa/formats/aarch64.isa b/src/arch/arm/isa/formats/aarch64.isa
index 9574012..a55d0dd 100644
--- a/src/arch/arm/isa/formats/aarch64.isa
+++ b/src/arch/arm/isa/formats/aarch64.isa
@@ -62,11 +62,11 @@
StaticInstPtr
decodeDataProcImm(ExtMachInst machInst)
{
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rdsp = makeSP(rd);
- IntRegIndex rdzr = makeZero(rd);
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rdsp = makeSP(rd);
+ RegIndex rdzr = makeZero(rd);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
uint8_t opc = bits(machInst, 30, 29);
bool sf = bits(machInst, 31);
@@ -81,9 +81,10 @@
uint64_t immhi = bits(machInst, 23, 5);
uint64_t imm = (immlo << 0) | (immhi << 2);
if (bits(machInst, 31) == 0)
- return new AdrXImm(machInst, rdzr, INTREG_ZERO, sext<21>(imm));
+ return new AdrXImm(machInst, rdzr, int_reg::Zero,
+ sext<21>(imm));
else
- return new AdrpXImm(machInst, rdzr, INTREG_ZERO,
+ return new AdrpXImm(machInst, rdzr, int_reg::Zero,
sext<33>(imm << 12));
}
case 0x2:
@@ -157,8 +158,8 @@
}
case 0x5:
{
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rdzr = makeZero(rd);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rdzr = makeZero(rd);
uint32_t imm16 = bits(machInst, 20, 5);
uint32_t hw = bits(machInst, 22, 21);
switch (opc) {
@@ -191,7 +192,7 @@
}
case 0x7:
{
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
if (opc || bits(machInst, 21))
return new Unknown64(machInst);
else
@@ -220,7 +221,7 @@
}
case 0x1:
{
- IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rt = (RegIndex)(uint8_t)bits(machInst, 4, 0);
if (bits(machInst, 25) == 0) {
int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
if (bits(machInst, 24) == 0)
@@ -287,7 +288,7 @@
uint8_t crn = bits(machInst, 15, 12);
uint8_t crm = bits(machInst, 11, 8);
uint8_t op2 = bits(machInst, 7, 5);
- IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rt = (RegIndex)(uint8_t)bits(machInst, 4, 0);
switch (op0) {
case 0x0:
// early out for TME
@@ -323,23 +324,23 @@
case 0x5:
return new SevlInst(machInst);
case 0x7:
- return new Xpaclri(machInst, INTREG_X30);
+ return new Xpaclri(machInst, int_reg::X30);
}
break;
case 0x1:
switch (op2) {
case 0x0:
- return new Pacia1716(machInst, INTREG_X17,
- INTREG_X16);
+ return new Pacia1716(machInst, int_reg::X17,
+ int_reg::X16);
case 0x2:
- return new Pacib1716(machInst, INTREG_X17,
- INTREG_X16);
+ return new Pacib1716(machInst, int_reg::X17,
+ int_reg::X16);
case 0x4:
- return new Autia1716(machInst, INTREG_X17,
- INTREG_X16);
+ return new Autia1716(machInst, int_reg::X17,
+ int_reg::X16);
case 0x6:
- return new Autib1716(machInst, INTREG_X17,
- INTREG_X16);
+ return new Autib1716(machInst, int_reg::X17,
+ int_reg::X16);
}
break;
case 0x2:
@@ -362,28 +363,28 @@
switch (op2) {
case 0x0:
return new Paciaz(machInst,
- INTREG_X30, INTREG_ZERO);
+ int_reg::X30, int_reg::Zero);
case 0x1:
return new Paciasp(machInst,
- INTREG_X30, INTREG_SPX);
+ int_reg::X30, int_reg::Spx);
case 0x2:
return new Pacibz(machInst,
- INTREG_X30, INTREG_ZERO);
+ int_reg::X30, int_reg::Zero);
case 0x3:
return new Pacibsp(machInst,
- INTREG_X30, INTREG_SPX);
+ int_reg::X30, int_reg::Spx);
case 0x4:
return new Autiaz(machInst,
- INTREG_X30, INTREG_ZERO);
+ int_reg::X30, int_reg::Zero);
case 0x5:
return new Autiasp(machInst,
- INTREG_X30, INTREG_SPX);
+ int_reg::X30, int_reg::Spx);
case 0x6:
return new Autibz(machInst,
- INTREG_X30, INTREG_ZERO);
+ int_reg::X30, int_reg::Zero);
case 0x7:
return new Autibsp(machInst,
- INTREG_X30, INTREG_SPX);
+ int_reg::X30, int_reg::Spx);
}
break;
case 0x4:
@@ -493,13 +494,15 @@
} else if (miscRegInfo[miscReg][MISCREG_IMPLEMENTED]) {
if (miscReg == MISCREG_NZCV) {
if (read)
- return new MrsNZCV64(machInst, rt, (IntRegIndex) miscReg);
+ return new MrsNZCV64(machInst, rt, miscReg);
else
- return new MsrNZCV64(machInst, (IntRegIndex) miscReg, rt);
+ return new MsrNZCV64(machInst, miscReg, rt);
}
- uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn, crm, op2, rt);
+ uint32_t iss = msrMrs64IssBuild(read, op0, op1, crn,
+ crm, op2, rt);
if (read) {
- StaticInstPtr si = new Mrs64(machInst, rt, miscReg, iss);
+ StaticInstPtr si = new Mrs64(machInst, rt, miscReg,
+ iss);
if (miscRegInfo[miscReg][MISCREG_UNVERIFIABLE])
si->setFlag(StaticInst::IsUnverifiable);
return si;
@@ -578,8 +581,8 @@
uint8_t opc = bits(machInst, 24, 21);
uint8_t op2 = bits(machInst, 20, 16);
uint8_t op3 = bits(machInst, 15, 12);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 4, 0);
uint8_t op4 = bits(machInst, 4, 0);
if (op2 != 0x1f || op3 != 0x0)
return new Unknown64(machInst);
@@ -665,10 +668,10 @@
uint8_t opc = bits(machInst, 14, 12);
uint8_t o3 = bits(machInst, 15);
uint8_t size_ar = bits(machInst, 23, 22)<<0 | bits(machInst, 31, 30)<<2;
- IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
- IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rt = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
+ RegIndex rs = (RegIndex)(uint8_t)bits(machInst, 20, 16);
uint8_t A_rt = bits(machInst, 4, 0)<<0 | bits(machInst, 23)<<5;
switch(opc) {
@@ -1222,11 +1225,11 @@
if (bits(machInst, 26) == 0) {
if (bits(machInst, 24) != 0)
return new Unknown64(machInst);
- IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
- IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
- IntRegIndex rs = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rt = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
+ RegIndex rt2 = (RegIndex)(uint8_t)bits(machInst, 14, 10);
+ RegIndex rs = (RegIndex)(uint8_t)bits(machInst, 20, 16);
uint8_t opc = (bits(machInst, 15) << 0) |
(bits(machInst, 23, 21) << 1);
uint8_t size = bits(machInst, 31, 30);
@@ -1430,7 +1433,7 @@
uint8_t switchVal = (bits(machInst, 26) << 0) |
(bits(machInst, 31, 30) << 1);
int64_t imm = sext<19>(bits(machInst, 23, 5)) << 2;
- IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 4, 0);
switch (switchVal) {
case 0x0:
return new LDRWL64_LIT(machInst, rt, imm);
@@ -1468,9 +1471,9 @@
uint8_t type = bits(machInst, 24, 23);
int64_t imm = sext<7>(bits(machInst, 21, 15)) * size;
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rt = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rt2 = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rt = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rt2 = (RegIndex)(uint8_t)bits(machInst, 14, 10);
bool noAlloc = (type == 0);
bool signExt = !noAlloc && !fp && opc == 1;
@@ -1515,9 +1518,9 @@
(bits(machInst, 31, 30) << 3);
if (bits(machInst, 24) == 1) {
uint64_t imm12 = bits(machInst, 21, 10);
- IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
+ RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
switch (switchVal) {
case 0x00:
return new STRB64_IMM(machInst, rt, rnsp, imm12);
@@ -1579,11 +1582,11 @@
{
if ((switchVal & 0x7) == 0x2 &&
bits(machInst, 20, 12) == 0x1fc) {
- IntRegIndex rt = (IntRegIndex)(uint32_t)
+ RegIndex rt = (RegIndex)(uint32_t)
bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)
+ RegIndex rn = (RegIndex)(uint32_t)
bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
+ RegIndex rnsp = makeSP(rn);
uint8_t size = bits(machInst, 31, 30);
switch (size) {
case 0x0:
@@ -1604,9 +1607,9 @@
case 0x1:
case 0x3:
{
- IntRegIndex rt = (IntRegIndex)(uint32_t)
+ RegIndex rt = (RegIndex)(uint32_t)
bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)
+ RegIndex rn = (RegIndex)(uint32_t)
bits(machInst, 9, 5);
uint8_t s = bits(machInst, 22);
uint64_t imm9 = bits(machInst, 20, 12);
@@ -1634,12 +1637,12 @@
{
if (!bits(machInst, 14))
return new Unknown64(machInst);
- IntRegIndex rt = (IntRegIndex)(uint32_t)
+ RegIndex rt = (RegIndex)(uint32_t)
bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)
+ RegIndex rn = (RegIndex)(uint32_t)
bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
- IntRegIndex rm = (IntRegIndex)(uint32_t)
+ RegIndex rnsp = makeSP(rn);
+ RegIndex rm = (RegIndex)(uint32_t)
bits(machInst, 20, 16);
ArmExtendType type =
(ArmExtendType)(uint32_t)bits(machInst, 15, 13);
@@ -1730,11 +1733,11 @@
switch (bits(machInst, 11, 10)) {
case 0x0:
{
- IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
+ RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
uint64_t imm = sext<9>(bits(machInst, 20, 12));
switch (switchVal) {
case 0x00:
@@ -1794,11 +1797,11 @@
// bit 29:27=111, 25:24=00, 21=0, 11:10=01
case 0x1:
{
- IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
+ RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
uint64_t imm = sext<9>(bits(machInst, 20, 12));
switch (switchVal) {
case 0x00:
@@ -1855,11 +1858,11 @@
}
case 0x2:
{
- IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
+ RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
uint64_t imm = sext<9>(bits(machInst, 20, 12));
switch (switchVal) {
case 0x00:
@@ -1894,11 +1897,11 @@
}
case 0x3:
{
- IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
+ RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
uint64_t imm = sext<9>(bits(machInst, 20, 12));
switch (switchVal) {
case 0x00:
@@ -1984,10 +1987,10 @@
bool sf = bits(machInst, 31);
if (!sf && (imm6 & 0x20))
return new Unknown64(machInst);
- IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rdzr = makeZero(rd);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rdzr = makeZero(rd);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
switch (switchVal) {
case 0x0:
@@ -2021,10 +2024,10 @@
uint8_t imm6 = bits(machInst, 15, 10);
if (!bits(machInst, 31) && bits(imm6, 5))
return new Unknown64(machInst);
- IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rdzr = makeZero(rd);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rdzr = makeZero(rd);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
switch (switchVal) {
case 0x0:
return new AddXSReg(machInst, rdzr, rn, rm, imm6, type);
@@ -2043,12 +2046,12 @@
ArmExtendType type =
(ArmExtendType)(uint8_t)bits(machInst, 15, 13);
uint8_t imm3 = bits(machInst, 12, 10);
- IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rdsp = makeSP(rd);
- IntRegIndex rdzr = makeZero(rd);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rnsp = makeSP(rn);
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rdsp = makeSP(rd);
+ RegIndex rdzr = makeZero(rd);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rnsp = makeSP(rn);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
switch (switchVal) {
case 0x0:
@@ -2068,10 +2071,10 @@
{
if (bits(machInst, 21) == 1)
return new Unknown64(machInst);
- IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rdzr = makeZero(rd);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rdzr = makeZero(rd);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
switch (bits(machInst, 23, 22)) {
case 0x0:
{
@@ -2101,10 +2104,10 @@
ConditionCode cond =
(ConditionCode)(uint8_t)bits(machInst, 15, 12);
uint8_t flags = bits(machInst, 3, 0);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
if (bits(machInst, 11) == 0) {
- IntRegIndex rm =
- (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rm =
+ (RegIndex)(uint8_t)bits(machInst, 20, 16);
if (bits(machInst, 30) == 0) {
return new CcmnReg64(machInst, rn, rm, cond, flags);
} else {
@@ -2127,10 +2130,10 @@
}
uint8_t switchVal = (bits(machInst, 10) << 0) |
(bits(machInst, 30) << 1);
- IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rdzr = makeZero(rd);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rdzr = makeZero(rd);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
ConditionCode cond =
(ConditionCode)(uint8_t)bits(machInst, 15, 12);
switch (switchVal) {
@@ -2211,49 +2214,49 @@
case 0x8:
if (rn == 0x1f)
return new Paciza(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
case 0x9:
if (rn == 0x1f)
return new Pacizb(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
case 0xa:
if (rn == 0x1f)
return new Pacdza(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
case 0xb:
if (rn == 0x1f)
return new Pacdzb(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
case 0xc:
if (rn == 0x1f)
return new Autiza(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
case 0xd:
if (rn == 0x1f)
return new Autizb(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
case 0xe:
if (rn == 0x1f)
return new Autdza(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
case 0xf:
if (rn == 0x1f)
return new Autdzb(machInst, rd,
- INTREG_ZERO);
+ int_reg::Zero);
else
return new Unknown64(machInst);
default:
@@ -2307,11 +2310,11 @@
if (bits(machInst, 30, 29) != 0x0 ||
(bits(machInst, 23, 21) != 0 && bits(machInst, 31) == 0))
return new Unknown64(machInst);
- IntRegIndex rd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex rdzr = makeZero(rd);
- IntRegIndex rn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
- IntRegIndex ra = (IntRegIndex)(uint8_t)bits(machInst, 14, 10);
- IntRegIndex rm = (IntRegIndex)(uint8_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex rdzr = makeZero(rd);
+ RegIndex rn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex ra = (RegIndex)(uint8_t)bits(machInst, 14, 10);
+ RegIndex rm = (RegIndex)(uint8_t)bits(machInst, 20, 16);
switch (bits(machInst, 23, 21)) {
case 0x0:
if (bits(machInst, 15) == 0)
@@ -2412,10 +2415,10 @@
if (bits(machInst, 24) == 1) {
if (bits(machInst, 31) || bits(machInst, 29))
return new Unknown64(machInst);
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
- IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 14, 10);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 20, 16);
+ RegIndex ra = (RegIndex)(uint32_t)bits(machInst, 14, 10);
uint8_t switchVal = (bits(machInst, 23, 21) << 1) |
(bits(machInst, 15) << 0);
switch (switchVal) {
@@ -2445,8 +2448,8 @@
uint8_t switchVal = bits(machInst, 20, 16);
uint8_t type = bits(machInst, 23, 22);
uint8_t scale = bits(machInst, 15, 10);
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 9, 5);
if (bits(machInst, 18, 17) == 3 && scale != 0)
return new Unknown64(machInst);
// 30:24=0011110, 21=0
@@ -2530,8 +2533,8 @@
// 30=0, 28:24=11110, 21=1
uint8_t type = bits(machInst, 23, 22);
uint8_t imm8 = bits(machInst, 20, 13);
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 9, 5);
switch (bits(machInst, 11, 10)) {
case 0x0:
if (bits(machInst, 12) == 1) {
@@ -2566,7 +2569,7 @@
}
uint8_t switchVal = (bits(machInst, 4, 3) << 0) |
(bits(machInst, 22) << 2);
- IntRegIndex rm = (IntRegIndex)(uint32_t)
+ RegIndex rm = (RegIndex)(uint32_t)
bits(machInst, 20, 16);
// 28:23=000111100, 21=1, 15:10=001000, 2:0=000
switch (switchVal) {
@@ -2895,9 +2898,9 @@
bits(machInst, 23)) {
return new Unknown64(machInst);
}
- IntRegIndex rm = (IntRegIndex)(uint32_t) bits(machInst, 20, 16);
- IntRegIndex rn = (IntRegIndex)(uint32_t) bits(machInst, 9, 5);
- uint8_t imm = (IntRegIndex)(uint32_t) bits(machInst, 3, 0);
+ RegIndex rm = (RegIndex)(uint32_t) bits(machInst, 20, 16);
+ RegIndex rn = (RegIndex)(uint32_t) bits(machInst, 9, 5);
+ uint8_t imm = (RegIndex)(uint32_t) bits(machInst, 3, 0);
ConditionCode cond =
(ConditionCode)(uint8_t)(bits(machInst, 15, 12));
uint8_t switchVal = (bits(machInst, 4) << 0) |
@@ -2929,9 +2932,9 @@
bits(machInst, 23)) {
return new Unknown64(machInst);
}
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 20, 16);
uint8_t switchVal = (bits(machInst, 15, 12) << 0) |
(bits(machInst, 22) << 4);
switch (switchVal) {
@@ -2980,9 +2983,9 @@
if (bits(machInst, 31) || bits(machInst, 29))
return new Unknown64(machInst);
uint8_t type = bits(machInst, 23, 22);
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 20, 16);
ConditionCode cond =
(ConditionCode)(uint8_t)(bits(machInst, 15, 12));
if (type == 0) // FCSEL Sd = if cond then Sn else Sm
diff --git a/src/arch/arm/isa/formats/branch.isa b/src/arch/arm/isa/formats/branch.isa
index 7c726ef..ff6bfda 100644
--- a/src/arch/arm/isa/formats/branch.isa
+++ b/src/arch/arm/isa/formats/branch.isa
@@ -72,8 +72,8 @@
def format ArmBxClz() {{
decode_block = '''
{
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 15, 12);
if (OPCODE == 0x9) {
return new BxReg(machInst, rm,
(ConditionCode)(uint32_t)machInst.condCode);
@@ -88,7 +88,7 @@
def format ArmBlxReg() {{
decode_block = '''
- return new BlxReg(machInst, (IntRegIndex)(uint32_t)bits(machInst, 3, 0),
+ return new BlxReg(machInst, (RegIndex)(uint32_t)bits(machInst, 3, 0),
(ConditionCode)(uint32_t)machInst.condCode);
'''
}};
@@ -144,8 +144,8 @@
case 0x38:
case 0x39:
{
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
const uint8_t byteMask = bits(machInst, 11, 8);
const bool r = bits(machInst, 20);
if (bits(machInst, 5)) {
@@ -232,7 +232,7 @@
case 0x3c:
{
return new BxjReg(machInst,
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16),
+ (RegIndex)(uint32_t)bits(machInst, 19, 16),
COND_UC);
}
case 0x3d:
@@ -241,16 +241,16 @@
if (imm32 == 0) {
return new Eret(machInst);
} else {
- return new SubsImmPclr(machInst, INTREG_PC,
- INTREG_LR, imm32, false);
+ return new SubsImmPclr(machInst, int_reg::Pc,
+ int_reg::Lr, imm32, false);
}
}
case 0x3e:
case 0x3f:
{
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 11, 8);
const bool r = bits(machInst, 20);
if (bits(machInst, 5)) {
const uint8_t sysM = (bits(machInst, 4) << 4) |
diff --git a/src/arch/arm/isa/formats/crypto64.isa b/src/arch/arm/isa/formats/crypto64.isa
index 133b9c6..702d2ef 100644
--- a/src/arch/arm/isa/formats/crypto64.isa
+++ b/src/arch/arm/isa/formats/crypto64.isa
@@ -55,8 +55,8 @@
const auto opcode = bits(machInst, 16, 12);
const auto size = bits(machInst, 23, 22);
- IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
if (size) {
// UNALLOCATED
@@ -78,8 +78,8 @@
const auto opcode = bits(machInst, 16, 12);
const auto size = bits(machInst, 23, 22);
- IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
if (size) {
// UNALLOCATED
@@ -100,9 +100,9 @@
const auto opcode = bits(machInst, 14, 12);
const auto size = bits(machInst, 23, 22);
- IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
if (size) {
// UNALLOCATED
diff --git a/src/arch/arm/isa/formats/data.isa b/src/arch/arm/isa/formats/data.isa
index 33d8d0f..89d8cb8 100644
--- a/src/arch/arm/isa/formats/data.isa
+++ b/src/arch/arm/isa/formats/data.isa
@@ -38,13 +38,13 @@
{
const uint32_t op1 = bits(machInst, 22, 20);
const uint32_t op2 = bits(machInst, 7, 5);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex ra = (RegIndex)(uint32_t)bits(machInst, 15, 12);
if (op1 == 0 && op2 == 0) {
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 11, 8);
if (ra == 0xf) {
return new Usad8(machInst, rd, rn, rm);
} else {
@@ -74,7 +74,7 @@
def format ArmDataProcReg() {{
pclr = '''
- if (%(dest)s == INTREG_PC) {
+ if (%(dest)s == int_reg::Pc) {
return new %(className)ssRegPclr(machInst, %(dest)s,
%(op1)s, rm, imm5,
type);
@@ -109,11 +109,11 @@
if useDest:
dest = "rd"
else:
- dest = "INTREG_ZERO"
+ dest = "int_reg::Zero"
if useOp1:
op1 = "rn"
else:
- op1 = "INTREG_ZERO"
+ op1 = "int_reg::Zero"
global instDecode, pclrCode
substDict = { "className": mnem.capitalize(),
"opcode": opcode,
@@ -131,10 +131,10 @@
const bool setCc = (bits(machInst, 20) == 1);
const uint32_t imm5 = bits(machInst, 11, 7);
const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 6, 5);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
- const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
- const IntRegIndex rm = (IntRegIndex)(uint32_t)RM;
- const IntRegIndex rs = (IntRegIndex)(uint32_t)RS;
+ const RegIndex rd = (RegIndex)(uint32_t)RD;
+ const RegIndex rn = (RegIndex)(uint32_t)RN;
+ const RegIndex rm = (RegIndex)(uint32_t)RM;
+ const RegIndex rs = (RegIndex)(uint32_t)RS;
switch (OPCODE) {
'''
decode_block += instCode(0x0, "and")
@@ -168,20 +168,20 @@
const uint32_t a = bits(machInst, 19, 16);
const uint32_t op2 = bits(machInst, 7, 5);
if (bits(op2, 0) == 0) {
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
const uint32_t satImm = bits(machInst, 20, 16);
const uint32_t imm = bits(machInst, 11, 7);
const ArmShiftType type =
(ArmShiftType)(uint32_t)bits(machInst, 6, 5);
if (op1 == 0) {
if (type) {
- return new PkhtbReg(machInst, rd, (IntRegIndex)a,
+ return new PkhtbReg(machInst, rd, (RegIndex)a,
rn, imm, type);
} else {
- return new PkhbtReg(machInst, rd, (IntRegIndex)a,
+ return new PkhbtReg(machInst, rd, (RegIndex)a,
rn, imm, type);
}
} else if (bits(op1, 2, 1) == 1) {
@@ -194,12 +194,12 @@
switch (op1) {
case 0x0:
{
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
if (op2 == 0x3) {
const uint32_t rotation =
(uint32_t)bits(machInst, 11, 10) << 3;
@@ -215,19 +215,19 @@
break;
case 0x2:
if (op2 == 0x1) {
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
const uint32_t satImm = bits(machInst, 20, 16);
return new Ssat16(machInst, rd, satImm + 1, rn);
} else if (op2 == 0x3) {
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t rotation =
(uint32_t)bits(machInst, 11, 10) << 3;
if (a == 0xf) {
@@ -239,16 +239,16 @@
break;
case 0x3:
if (op2 == 0x1) {
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
return new Rev(machInst, rd, rm);
} else if (op2 == 0x3) {
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t rotation =
(uint32_t)bits(machInst, 11, 10) << 3;
if (a == 0xf) {
@@ -257,19 +257,19 @@
return new Sxtah(machInst, rd, rn, rm, rotation);
}
} else if (op2 == 0x5) {
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
return new Rev16(machInst, rd, rm);
}
break;
case 0x4:
if (op2 == 0x3) {
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t rotation =
(uint32_t)bits(machInst, 11, 10) << 3;
if (a == 0xf) {
@@ -281,19 +281,19 @@
break;
case 0x6:
if (op2 == 0x1) {
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
const uint32_t satImm = bits(machInst, 20, 16);
return new Usat16(machInst, rd, satImm, rn);
} else if (op2 == 0x3) {
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t rotation =
(uint32_t)bits(machInst, 11, 10) << 3;
if (a == 0xf) {
@@ -305,12 +305,12 @@
break;
case 0x7:
{
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
if (op2 == 0x1) {
return new Rbit(machInst, rd, rm);
} else if (op2 == 0x3) {
@@ -337,9 +337,9 @@
{
const uint32_t op1 = bits(machInst, 21, 20);
const uint32_t op2 = bits(machInst, 7, 5);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
if (bits(machInst, 22) == 0) {
switch (op1) {
case 0x1:
@@ -450,13 +450,13 @@
def format ArmDataProcImm() {{
pclr = '''
- if (%(dest)s == INTREG_PC) {
+ if (%(dest)s == int_reg::Pc) {
return new %(className)ssImmPclr(machInst, %(dest)s,
%(op1)s, imm, false);
} else
'''
adr = '''
- if (%(op1)s == INTREG_PC) {
+ if (%(op1)s == int_reg::Pc) {
return new AdrImm(machInst, %(dest)s, %(add)s,
imm, false);
} else
@@ -482,11 +482,11 @@
if useDest:
dest = "rd"
else:
- dest = "INTREG_ZERO"
+ dest = "int_reg::Zero"
if useOp1:
op1 = "rn"
else:
- op1 = "INTREG_ZERO"
+ op1 = "int_reg::Zero"
substDict = { "className": mnem.capitalize(),
"opcode": opcode,
"dest": dest,
@@ -516,15 +516,15 @@
const uint32_t rotation = (bits(machInst, 11, 8) << 1);
const bool rotC = (rotation != 0);
const uint32_t imm = rotate_imm(unrotated, rotation);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)RD;
- const IntRegIndex rn = (IntRegIndex)(uint32_t)RN;
+ const RegIndex rd = (RegIndex)(uint32_t)RD;
+ const RegIndex rn = (RegIndex)(uint32_t)RN;
switch (OPCODE) {
'''
decode_block += instCode(0x0, "and")
decode_block += instCode(0x1, "eor")
- decode_block += adrCode(0x2, "sub", add="(IntRegIndex)0")
+ decode_block += adrCode(0x2, "sub", add="(RegIndex)0")
decode_block += instCode(0x3, "rsb")
- decode_block += adrCode(0x4, "add", add="(IntRegIndex)1")
+ decode_block += adrCode(0x4, "add", add="(RegIndex)1")
decode_block += instCode(0x5, "adc")
decode_block += instCode(0x6, "sbc")
decode_block += instCode(0x7, "rsc")
@@ -547,9 +547,9 @@
def format ArmSatAddSub() {{
decode_block = '''
{
- IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
switch (OPCODE) {
case 0x8:
return new QaddRegCc(machInst, rd, rm, rn, 0, LSL);
@@ -570,50 +570,50 @@
decode_block = '''
{
const uint32_t op1 = bits(machInst, 23, 20);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
const uint32_t op2 = bits(machInst, 7, 4);
if (bits(machInst, 15, 12) != 0xf) {
return new Unknown(machInst);
}
if (bits(op1, 3) != 1) {
if (op2 == 0) {
- IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
switch (bits(op1, 2, 0)) {
case 0x0:
return new MovRegReg(machInst, rd,
- INTREG_ZERO, rn, rm, LSL);
+ int_reg::Zero, rn, rm, LSL);
case 0x1:
return new MovRegRegCc(machInst, rd,
- INTREG_ZERO, rn, rm, LSL);
+ int_reg::Zero, rn, rm, LSL);
case 0x2:
return new MovRegReg(machInst, rd,
- INTREG_ZERO, rn, rm, LSR);
+ int_reg::Zero, rn, rm, LSR);
case 0x3:
return new MovRegRegCc(machInst, rd,
- INTREG_ZERO, rn, rm, LSR);
+ int_reg::Zero, rn, rm, LSR);
case 0x4:
return new MovRegReg(machInst, rd,
- INTREG_ZERO, rn, rm, ASR);
+ int_reg::Zero, rn, rm, ASR);
case 0x5:
return new MovRegRegCc(machInst, rd,
- INTREG_ZERO, rn, rm, ASR);
+ int_reg::Zero, rn, rm, ASR);
case 0x6:
return new MovRegReg(machInst, rd,
- INTREG_ZERO, rn, rm, ROR);
+ int_reg::Zero, rn, rm, ROR);
case 0x7:
return new MovRegRegCc(machInst, rd,
- INTREG_ZERO, rn, rm, ROR);
+ int_reg::Zero, rn, rm, ROR);
default:
GEM5_UNREACHABLE;
}
} else if (bits(op2, 3) == 0) {
return new Unknown(machInst);
} else {
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t rotation =
(uint32_t)bits(machInst, 5, 4) << 3;
switch (bits(op1, 2, 0)) {
@@ -659,10 +659,10 @@
}
} else {
if (bits(op2, 3) == 0) {
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
if (bits(op2, 2) == 0x0) {
const uint32_t op1 = bits(machInst, 22, 20);
const uint32_t op2 = bits(machInst, 5, 4);
@@ -785,10 +785,10 @@
} else if (bits(op1, 3, 2) == 0x2 && bits(op2, 3, 2) == 0x2) {
const uint32_t op1 = bits(machInst, 22, 20);
const uint32_t op2 = bits(machInst, 5, 4);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
switch (op1) {
case 0x0:
switch (op2) {
@@ -832,10 +832,10 @@
} else if (bits(op1, 3, 2) == 0x3 && bits(op2, 3, 2) == 0x2) {
const uint32_t op1 = bits(machInst, 22, 20);
const uint32_t op2 = bits(machInst, 5, 4);
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
switch (op1) {
case 0x4:
switch (op2) {
@@ -871,28 +871,31 @@
const uint32_t imm5 = bits(machInst, 10, 6);
const uint32_t imm3 = bits(machInst, 8, 6);
const uint32_t imm8 = bits(machInst, 7, 0);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
- const IntRegIndex rd8 = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 8, 6);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 2, 0);
+ const RegIndex rd8 = (RegIndex)(uint32_t)bits(machInst, 10, 8);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 5, 3);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 8, 6);
switch (bits(machInst, 13, 11)) {
case 0x0: // lsl
if (machInst.itstateMask) {
- return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
+ return new MovReg(machInst, rd, int_reg::Zero, rn, imm5, LSL);
} else {
- return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSL);
+ return new MovRegCc(machInst, rd, int_reg::Zero, rn, imm5,
+ LSL);
}
case 0x1: // lsr
if (machInst.itstateMask) {
- return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
+ return new MovReg(machInst, rd, int_reg::Zero, rn, imm5, LSR);
} else {
- return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, LSR);
+ return new MovRegCc(machInst, rd, int_reg::Zero, rn, imm5,
+ LSR);
}
case 0x2: // asr
if (machInst.itstateMask) {
- return new MovReg(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
+ return new MovReg(machInst, rd, int_reg::Zero, rn, imm5, ASR);
} else {
- return new MovRegCc(machInst, rd, INTREG_ZERO, rn, imm5, ASR);
+ return new MovRegCc(machInst, rd, int_reg::Zero, rn, imm5,
+ ASR);
}
case 0x3:
switch (bits(machInst, 10, 9)) {
@@ -925,12 +928,12 @@
}
case 0x4:
if (machInst.itstateMask) {
- return new MovImm(machInst, rd8, INTREG_ZERO, imm8, false);
+ return new MovImm(machInst, rd8, int_reg::Zero, imm8, false);
} else {
- return new MovImmCc(machInst, rd8, INTREG_ZERO, imm8, false);
+ return new MovImmCc(machInst, rd8, int_reg::Zero, imm8, false);
}
case 0x5:
- return new CmpImmCc(machInst, INTREG_ZERO, rd8, imm8, true);
+ return new CmpImmCc(machInst, int_reg::Zero, rd8, imm8, true);
case 0x6:
if (machInst.itstateMask) {
return new AddImm(machInst, rd8, rd8, imm8, true);
@@ -953,8 +956,8 @@
def format Thumb16DataProcessing() {{
decode_block = '''
{
- const IntRegIndex rdn = (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
+ const RegIndex rdn = (RegIndex)(uint32_t)bits(machInst, 2, 0);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 5, 3);
switch (bits(machInst, 9, 6)) {
case 0x0:
if (machInst.itstateMask) {
@@ -971,26 +974,26 @@
case 0x2: //lsl
if (machInst.itstateMask) {
return new MovRegReg(machInst, rdn,
- INTREG_ZERO, rdn, rm, LSL);
+ int_reg::Zero, rdn, rm, LSL);
} else {
return new MovRegRegCc(machInst, rdn,
- INTREG_ZERO, rdn, rm, LSL);
+ int_reg::Zero, rdn, rm, LSL);
}
case 0x3: //lsr
if (machInst.itstateMask) {
return new MovRegReg(machInst, rdn,
- INTREG_ZERO, rdn, rm, LSR);
+ int_reg::Zero, rdn, rm, LSR);
} else {
return new MovRegRegCc(machInst, rdn,
- INTREG_ZERO, rdn, rm, LSR);
+ int_reg::Zero, rdn, rm, LSR);
}
case 0x4: //asr
if (machInst.itstateMask) {
return new MovRegReg(machInst, rdn,
- INTREG_ZERO, rdn, rm, ASR);
+ int_reg::Zero, rdn, rm, ASR);
} else {
return new MovRegRegCc(machInst, rdn,
- INTREG_ZERO, rdn, rm, ASR);
+ int_reg::Zero, rdn, rm, ASR);
}
case 0x5:
if (machInst.itstateMask) {
@@ -1007,13 +1010,13 @@
case 0x7: // ror
if (machInst.itstateMask) {
return new MovRegReg(machInst, rdn,
- INTREG_ZERO, rdn, rm, ROR);
+ int_reg::Zero, rdn, rm, ROR);
} else {
return new MovRegRegCc(machInst, rdn,
- INTREG_ZERO, rdn, rm, ROR);
+ int_reg::Zero, rdn, rm, ROR);
}
case 0x8:
- return new TstRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+ return new TstRegCc(machInst, int_reg::Zero, rdn, rm, 0, LSL);
case 0x9:
if (machInst.itstateMask) {
return new RsbImm(machInst, rdn, rm, 0, true);
@@ -1021,9 +1024,9 @@
return new RsbImmCc(machInst, rdn, rm, 0, true);
}
case 0xa:
- return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+ return new CmpRegCc(machInst, int_reg::Zero, rdn, rm, 0, LSL);
case 0xb:
- return new CmnRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+ return new CmnRegCc(machInst, int_reg::Zero, rdn, rm, 0, LSL);
case 0xc:
if (machInst.itstateMask) {
return new OrrReg(machInst, rdn, rdn, rm, 0, LSL);
@@ -1044,9 +1047,9 @@
}
case 0xf:
if (machInst.itstateMask) {
- return new MvnReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
+ return new MvnReg(machInst, rdn, int_reg::Zero, rm, 0, LSL);
} else {
- return new MvnRegCc(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
+ return new MvnRegCc(machInst, rdn, int_reg::Zero, rm, 0, LSL);
}
default:
GEM5_UNREACHABLE;
@@ -1058,25 +1061,25 @@
def format Thumb16SpecDataAndBx() {{
decode_block = '''
{
- const IntRegIndex rdn =
- (IntRegIndex)(uint32_t)(bits(machInst, 2, 0) |
+ const RegIndex rdn =
+ (RegIndex)(uint32_t)(bits(machInst, 2, 0) |
(bits(machInst, 7) << 3));
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 6, 3);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 6, 3);
switch (bits(machInst, 9, 8)) {
case 0x0:
return new AddReg(machInst, rdn, rdn, rm, 0, LSL);
case 0x1:
- return new CmpRegCc(machInst, INTREG_ZERO, rdn, rm, 0, LSL);
+ return new CmpRegCc(machInst, int_reg::Zero, rdn, rm, 0, LSL);
case 0x2:
- return new MovReg(machInst, rdn, INTREG_ZERO, rm, 0, LSL);
+ return new MovReg(machInst, rdn, int_reg::Zero, rm, 0, LSL);
case 0x3:
if (bits(machInst, 7) == 0) {
return new BxReg(machInst,
- (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
+ (RegIndex)(uint32_t)bits(machInst, 6, 3),
COND_UC);
} else {
return new BlxReg(machInst,
- (IntRegIndex)(uint32_t)bits(machInst, 6, 3),
+ (RegIndex)(uint32_t)bits(machInst, 6, 3),
COND_UC);
}
default:
@@ -1089,9 +1092,9 @@
def format Thumb16Adr() {{
decode_block = '''
{
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 10, 8);
const uint32_t imm8 = bits(machInst, 7, 0) << 2;
- return new AdrImm(machInst, rd, (IntRegIndex)1, imm8, false);
+ return new AdrImm(machInst, rd, (RegIndex)1, imm8, false);
}
'''
}};
@@ -1099,9 +1102,9 @@
def format Thumb16AddSp() {{
decode_block = '''
{
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 10, 8);
const uint32_t imm8 = bits(machInst, 7, 0) << 2;
- return new AddImm(machInst, rd, INTREG_SP, imm8, true);
+ return new AddImm(machInst, rd, int_reg::Sp, imm8, true);
}
'''
}};
@@ -1115,8 +1118,7 @@
const uint8_t byteMask = bits(machInst, 19, 16);
switch (OPCODE) {
case 0x8:
- return new MovImm(machInst, (IntRegIndex)(uint32_t)RD,
- (IntRegIndex)INTREG_ZERO,
+ return new MovImm(machInst, (RegIndex)RD, int_reg::Zero,
bits(machInst, 11, 0) | (bits(machInst, 19, 16) << 12),
false);
case 0x9:
@@ -1158,8 +1160,8 @@
{
const uint32_t timm = (bits(machInst, 19, 16) << 12) |
bits(machInst, 11, 0);
- return new MovtImm(machInst, (IntRegIndex)(uint32_t)RD,
- (IntRegIndex)(uint32_t)RD, timm, true);
+ return new MovtImm(machInst, (RegIndex)(uint32_t)RD,
+ (RegIndex)(uint32_t)RD, timm, true);
}
case 0xb:
return new MsrSpsrImm(machInst, imm, byteMask);
@@ -1176,18 +1178,18 @@
switch (bits(machInst, 11, 8)) {
case 0x0:
if (bits(machInst, 7)) {
- return new SubImm(machInst, INTREG_SP, INTREG_SP,
+ return new SubImm(machInst, int_reg::Sp, int_reg::Sp,
bits(machInst, 6, 0) << 2, true);
} else {
- return new AddImm(machInst, INTREG_SP, INTREG_SP,
+ return new AddImm(machInst, int_reg::Sp, int_reg::Sp,
bits(machInst, 6, 0) << 2, true);
}
case 0x2:
{
- const IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
+ const RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 2, 0);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 5, 3);
switch (bits(machInst, 7, 6)) {
case 0x0:
return new Sxth(machInst, rd, 0, rm);
@@ -1206,13 +1208,13 @@
return new Cbz(machInst,
(bits(machInst, 9) << 6) |
(bits(machInst, 7, 3) << 1),
- (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
+ (RegIndex)(uint32_t)bits(machInst, 2, 0));
case 0x4:
case 0x5:
{
const uint32_t m = bits(machInst, 8);
const uint32_t regList = bits(machInst, 7, 0) | (m << 14);
- return new LdmStm(machInst, INTREG_SP, false, false, false,
+ return new LdmStm(machInst, int_reg::Sp, false, false, false,
true, false, regList);
}
case 0x6:
@@ -1234,10 +1236,10 @@
if (op1 == 0x2) {
return new Hlt(machInst, bits(machInst, 5, 0));
} else {
- IntRegIndex rd =
- (IntRegIndex)(uint32_t)bits(machInst, 2, 0);
- IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 5, 3);
+ RegIndex rd =
+ (RegIndex)(uint32_t)bits(machInst, 2, 0);
+ RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 5, 3);
switch (op1) {
case 0x0:
@@ -1257,13 +1259,13 @@
return new Cbnz(machInst,
(bits(machInst, 9) << 6) |
(bits(machInst, 7, 3) << 1),
- (IntRegIndex)(uint32_t)bits(machInst, 2, 0));
+ (RegIndex)(uint32_t)bits(machInst, 2, 0));
case 0xc:
case 0xd:
{
const uint32_t p = bits(machInst, 8);
const uint32_t regList = bits(machInst, 7, 0) | (p << 15);
- return new LdmStm(machInst, INTREG_SP, true, true, false,
+ return new LdmStm(machInst, int_reg::Sp, true, true, false,
true, true, regList);
}
case 0xe:
@@ -1312,8 +1314,8 @@
{
const uint32_t op = bits(machInst, 24, 21);
const bool s = (bits(machInst, 20) == 1);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 11, 8);
const uint32_t ctrlImm = bits(machInst.instBits, 26) << 3 |
bits(machInst, 14, 12);
const bool rotC = ctrlImm > 3;
@@ -1321,7 +1323,7 @@
const uint32_t imm = modified_imm(ctrlImm, dataImm);
switch (op) {
case 0x0:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(tst)s
} else {
%(and)s
@@ -1329,25 +1331,25 @@
case 0x1:
%(bic)s
case 0x2:
- if (rn == INTREG_PC) {
+ if (rn == int_reg::Pc) {
%(mov)s
} else {
%(orr)s
}
case 0x3:
- if (rn == INTREG_PC) {
+ if (rn == int_reg::Pc) {
%(mvn)s
} else {
%(orn)s
}
case 0x4:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(teq)s
} else {
%(eor)s
}
case 0x8:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(cmn)s
} else {
%(add)s
@@ -1357,7 +1359,7 @@
case 0xb:
%(sbc)s
case 0xd:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(cmp)s
} else {
%(sub)s
@@ -1369,20 +1371,20 @@
}
}
''' % {
- "tst" : decInst("Tst", "INTREG_ZERO"),
+ "tst" : decInst("Tst", "int_reg::Zero"),
"and" : decInst("And"),
"bic" : decInst("Bic"),
- "mov" : decInst("Mov", op1="INTREG_ZERO"),
+ "mov" : decInst("Mov", op1="int_reg::Zero"),
"orr" : decInst("Orr"),
- "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
+ "mvn" : decInst("Mvn", op1="int_reg::Zero"),
"orn" : decInst("Orn"),
- "teq" : decInst("Teq", dest="INTREG_ZERO"),
+ "teq" : decInst("Teq", dest="int_reg::Zero"),
"eor" : decInst("Eor"),
- "cmn" : decInst("Cmn", dest="INTREG_ZERO"),
+ "cmn" : decInst("Cmn", dest="int_reg::Zero"),
"add" : decInst("Add"),
"adc" : decInst("Adc"),
"sbc" : decInst("Sbc"),
- "cmp" : decInst("Cmp", dest="INTREG_ZERO"),
+ "cmp" : decInst("Cmp", dest="int_reg::Zero"),
"sub" : decInst("Sub"),
"rsb" : decInst("Rsb")
}
@@ -1392,8 +1394,8 @@
decode_block = '''
{
const uint32_t op = bits(machInst, 24, 20);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 11, 8);
switch (op) {
case 0x0:
{
@@ -1401,7 +1403,7 @@
(bits(machInst, 14, 12) << 8) |
(bits(machInst, 26) << 11);
if (rn == 0xf) {
- return new AdrImm(machInst, rd, (IntRegIndex)1,
+ return new AdrImm(machInst, rd, (RegIndex)1,
imm, false);
} else {
return new AddImm(machInst, rd, rn, imm, true);
@@ -1413,7 +1415,7 @@
(bits(machInst, 14, 12) << 8) |
(bits(machInst, 26) << 11) |
(bits(machInst, 19, 16) << 12);
- return new MovImm(machInst, rd, INTREG_ZERO, imm, true);
+ return new MovImm(machInst, rd, int_reg::Zero, imm, true);
}
case 0xa:
{
@@ -1421,7 +1423,7 @@
(bits(machInst, 14, 12) << 8) |
(bits(machInst, 26) << 11);
if (rn == 0xf) {
- return new AdrImm(machInst, rd, (IntRegIndex)0,
+ return new AdrImm(machInst, rd, (RegIndex)0,
imm, false);
} else {
return new SubImm(machInst, rd, rn, imm, true);
@@ -1514,15 +1516,15 @@
{
const uint32_t op = bits(machInst, 24, 21);
const bool s = (bits(machInst, 20) == 1);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t amt = (bits(machInst, 14, 12) << 2) |
bits(machInst, 7, 6);
const ArmShiftType type = (ArmShiftType)(uint32_t)bits(machInst, 5, 4);
switch (op) {
case 0x0:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(tst)s
} else {
%(and)s
@@ -1530,19 +1532,19 @@
case 0x1:
%(bic)s
case 0x2:
- if (rn == INTREG_PC) {
+ if (rn == int_reg::Pc) {
%(mov)s
} else {
%(orr)s
}
case 0x3:
- if (rn == INTREG_PC) {
+ if (rn == int_reg::Pc) {
%(mvn)s
} else {
%(orn)s
}
case 0x4:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(teq)s
} else {
%(eor)s
@@ -1554,7 +1556,7 @@
return new PkhbtReg(machInst, rd, rn, rm, amt, type);
}
case 0x8:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(cmn)s
} else {
%(add)s
@@ -1564,7 +1566,7 @@
case 0xb:
%(sbc)s
case 0xd:
- if (rd == INTREG_PC) {
+ if (rd == int_reg::Pc) {
%(cmp)s
} else {
%(sub)s
@@ -1576,20 +1578,20 @@
}
}
''' % {
- "tst" : decInst("Tst", "INTREG_ZERO"),
+ "tst" : decInst("Tst", "int_reg::Zero"),
"and" : decInst("And"),
"bic" : decInst("Bic"),
- "mov" : decInst("Mov", op1="INTREG_ZERO"),
+ "mov" : decInst("Mov", op1="int_reg::Zero"),
"orr" : decInst("Orr"),
- "mvn" : decInst("Mvn", op1="INTREG_ZERO"),
+ "mvn" : decInst("Mvn", op1="int_reg::Zero"),
"orn" : decInst("Orn"),
- "teq" : decInst("Teq", "INTREG_ZERO"),
+ "teq" : decInst("Teq", "int_reg::Zero"),
"eor" : decInst("Eor"),
- "cmn" : decInst("Cmn", "INTREG_ZERO"),
+ "cmn" : decInst("Cmn", "int_reg::Zero"),
"add" : decInst("Add"),
"adc" : decInst("Adc"),
"sbc" : decInst("Sbc"),
- "cmp" : decInst("Cmp", "INTREG_ZERO"),
+ "cmp" : decInst("Cmp", "int_reg::Zero"),
"sub" : decInst("Sub"),
"rsb" : decInst("Rsb")
}
diff --git a/src/arch/arm/isa/formats/fp.isa b/src/arch/arm/isa/formats/fp.isa
index ce492c9..eac2ba0 100644
--- a/src/arch/arm/isa/formats/fp.isa
+++ b/src/arch/arm/isa/formats/fp.isa
@@ -343,11 +343,11 @@
uint8_t op_code = (bits(machInst, 25) << 1)
| bits(machInst, 21);
- IntRegIndex vd = (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ RegIndex vd = (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
- IntRegIndex vn = (IntRegIndex)(2 * (bits(machInst, 19, 16) |
+ RegIndex vn = (RegIndex)(2 * (bits(machInst, 19, 16) |
(bits(machInst, 7) << 4)));
- IntRegIndex vm = (IntRegIndex)(2 * (bits(machInst, 3, 0) |
+ RegIndex vm = (RegIndex)(2 * (bits(machInst, 3, 0) |
(bits(machInst, 5) << 4)));
bool q = bits (machInst, 6);
switch (op_code) {
@@ -397,7 +397,7 @@
return new VcmlaElemD<uint32_t>(machInst, vd, vn, vm,
index_fp);
} else {
- vm = (IntRegIndex)(uint8_t)(2* bits(machInst, 3, 0));
+ vm = (RegIndex)(uint8_t)(2* bits(machInst, 3, 0));
uint8_t index_fp = bits(machInst, 5);
if (q)
return new VcmlaElemQ<uint16_t>(machInst, vd, vn, vm,
@@ -423,14 +423,14 @@
const uint32_t opc = bits(machInst, 11, 8);
const bool o1 = bits(machInst, 4);
const uint32_t size = bits(machInst, 21, 20);
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ const RegIndex vd =
+ (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
- const IntRegIndex vn =
- (IntRegIndex)(2 * (bits(machInst, 19, 16) |
+ const RegIndex vn =
+ (RegIndex)(2 * (bits(machInst, 19, 16) |
(bits(machInst, 7) << 4)));
- const IntRegIndex vm =
- (IntRegIndex)(2 * (bits(machInst, 3, 0) |
+ const RegIndex vm =
+ (RegIndex)(2 * (bits(machInst, 3, 0) |
(bits(machInst, 5) << 4)));
const bool q = bits(machInst, 6);
if (q && ((vd & 0x1) || (vn & 0x1) || (vm & 0x1)))
@@ -905,8 +905,8 @@
static StaticInstPtr
decodeNeonOneRegModImm(ExtMachInst machInst)
{
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ const RegIndex vd =
+ (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
const bool q = bits(machInst, 6);
const bool op = bits(machInst, 5);
@@ -1015,11 +1015,11 @@
const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
const bool q = bits(machInst, 6);
const bool l = bits(machInst, 7);
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ const RegIndex vd =
+ (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
- const IntRegIndex vm =
- (IntRegIndex)(2 * (bits(machInst, 3, 0) |
+ const RegIndex vm =
+ (RegIndex)(2 * (bits(machInst, 3, 0) |
(bits(machInst, 5) << 4)));
unsigned imm6 = bits(machInst, 21, 16);
unsigned imm = ((l ? 1 : 0) << 6) | imm6;
@@ -1168,14 +1168,14 @@
{
const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
const uint32_t opc = bits(machInst, 11, 8);
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ const RegIndex vd =
+ (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
- const IntRegIndex vn =
- (IntRegIndex)(2 * (bits(machInst, 19, 16) |
+ const RegIndex vn =
+ (RegIndex)(2 * (bits(machInst, 19, 16) |
(bits(machInst, 7) << 4)));
- const IntRegIndex vm =
- (IntRegIndex)(2 * (bits(machInst, 3, 0) |
+ const RegIndex vm =
+ (RegIndex)(2 * (bits(machInst, 3, 0) |
(bits(machInst, 5) << 4)));
const unsigned size = bits(machInst, 21, 20);
switch (opc) {
@@ -1261,15 +1261,15 @@
const bool u = THUMB ? bits(machInst, 28) : bits(machInst, 24);
const uint32_t opc = bits(machInst, 11, 8);
const unsigned size = bits(machInst, 21, 20);
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ const RegIndex vd =
+ (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
- const IntRegIndex vn =
- (IntRegIndex)(2 * (bits(machInst, 19, 16) |
+ const RegIndex vn =
+ (RegIndex)(2 * (bits(machInst, 19, 16) |
(bits(machInst, 7) << 4)));
- const IntRegIndex vm = (size == 2) ?
- (IntRegIndex)(2 * bits(machInst, 3, 0)) :
- (IntRegIndex)(2 * bits(machInst, 2, 0));
+ const RegIndex vm = (size == 2) ?
+ (RegIndex)(2 * bits(machInst, 3, 0)) :
+ (RegIndex)(2 * bits(machInst, 2, 0));
const unsigned index = (size == 2) ? (unsigned)bits(machInst, 5) :
(bits(machInst, 3) | (bits(machInst, 5) << 1));
switch (opc) {
@@ -1568,11 +1568,11 @@
const uint32_t opc1 = bits(machInst, 17, 16);
const uint32_t b = bits(machInst, 10, 6);
const bool q = bits(machInst, 6);
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ const RegIndex vd =
+ (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
- const IntRegIndex vm =
- (IntRegIndex)(2 * (bits(machInst, 3, 0) |
+ const RegIndex vm =
+ (RegIndex)(2 * (bits(machInst, 3, 0) |
(bits(machInst, 5) << 4)));
const unsigned size = bits(machInst, 19, 18);
switch (opc1) {
@@ -1922,14 +1922,14 @@
return decodeNeonTwoRegScalar(machInst);
}
} else if ((a & 0x16) == 0x16) {
- const IntRegIndex vd =
- (IntRegIndex)(2 * (bits(machInst, 15, 12) |
+ const RegIndex vd =
+ (RegIndex)(2 * (bits(machInst, 15, 12) |
(bits(machInst, 22) << 4)));
- const IntRegIndex vn =
- (IntRegIndex)(2 * (bits(machInst, 19, 16) |
+ const RegIndex vn =
+ (RegIndex)(2 * (bits(machInst, 19, 16) |
(bits(machInst, 7) << 4)));
- const IntRegIndex vm =
- (IntRegIndex)(2 * (bits(machInst, 3, 0) |
+ const RegIndex vm =
+ (RegIndex)(2 * (bits(machInst, 3, 0) |
(bits(machInst, 5) << 4)));
if (!u) {
if (bits(c, 0) == 0) {
@@ -2013,7 +2013,7 @@
let {{
header_output = '''
bool
- wrongVLdmStmRegs(IntRegIndex start_reg, uint8_t count, bool single);
+ wrongVLdmStmRegs(RegIndex start_reg, uint8_t count, bool single);
StaticInstPtr
decodeExtensionRegLoadStore(ExtMachInst machInst);
@@ -2041,7 +2041,7 @@
const uint32_t opcode = bits(machInst, 24, 20);
const uint32_t offset = bits(machInst, 7, 0);
const bool single = (bits(machInst, 8) == 0);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
RegIndex vd = decodeFpVd(machInst, single ? 0x2 : 0x3, false);
switch (bits(opcode, 4, 3)) {
@@ -2052,10 +2052,10 @@
if ((bits(machInst, 7, 4) & 0xd) != 1) {
break;
}
- const IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rt2 =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt2 =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
const bool op = bits(machInst, 20);
uint32_t vm;
if (single) {
@@ -2066,9 +2066,9 @@
}
if (op) {
return new Vmov2Core2Reg(machInst, rt, rt2,
- (IntRegIndex)vm);
+ (RegIndex)vm);
} else {
- return new Vmov2Reg2Core(machInst, (IntRegIndex)vm,
+ return new Vmov2Reg2Core(machInst, (RegIndex)vm,
rt, rt2);
}
}
@@ -2176,40 +2176,40 @@
StaticInstPtr
decodeShortFpTransfer(ExtMachInst machInst);
- IntRegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt);
- IntRegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt);
- IntRegIndex decodeFpVn(ExtMachInst machInst, uint32_t size);
+ RegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt);
+ RegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt);
+ RegIndex decodeFpVn(ExtMachInst machInst, uint32_t size);
'''
decoder_output = '''
- IntRegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt)
+ RegIndex decodeFpVd(ExtMachInst machInst, uint32_t size, bool isInt)
{
if (!isInt and size == 3) {
- return (IntRegIndex)((bits(machInst, 22) << 5) |
+ return (RegIndex)((bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1));
} else {
- return (IntRegIndex)(bits(machInst, 22) |
+ return (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
}
}
- IntRegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt)
+ RegIndex decodeFpVm(ExtMachInst machInst, uint32_t size, bool isInt)
{
if (!isInt and size == 3) {
- return (IntRegIndex)((bits(machInst, 5) << 5) |
+ return (RegIndex)((bits(machInst, 5) << 5) |
(bits(machInst, 3, 0) << 1));
} else {
- return (IntRegIndex)(bits(machInst, 5) |
+ return (RegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
}
}
- IntRegIndex decodeFpVn(ExtMachInst machInst, uint32_t size)
+ RegIndex decodeFpVn(ExtMachInst machInst, uint32_t size)
{
if (size == 3) {
- return (IntRegIndex)((bits(machInst, 7) << 5) |
+ return (RegIndex)((bits(machInst, 7) << 5) |
(bits(machInst, 19, 16) << 1));
} else {
- return (IntRegIndex)(bits(machInst, 7) |
+ return (RegIndex)(bits(machInst, 7) |
(bits(machInst, 19, 16) << 1));
}
}
@@ -2222,10 +2222,10 @@
const uint32_t op3 = bits(machInst, 6);
const uint32_t rm = bits(machInst, 17, 16);
const uint32_t size = bits(machInst, 9, 8);
- IntRegIndex vd = decodeFpVd(machInst, size, false);
- IntRegIndex vm = decodeFpVm(machInst, size, false);
- IntRegIndex vdInt = decodeFpVd(machInst, size, true);
- IntRegIndex vn = decodeFpVn(machInst, size);
+ RegIndex vd = decodeFpVd(machInst, size, false);
+ RegIndex vm = decodeFpVm(machInst, size, false);
+ RegIndex vdInt = decodeFpVd(machInst, size, true);
+ RegIndex vn = decodeFpVn(machInst, size);
if (bits(machInst, 31, 24) == 0xFE && !bits(machInst, 4)) {
if (bits(op0, 3) == 0 && op2 != 0 && !op3){
ConditionCode cond;
@@ -2407,16 +2407,16 @@
if (a == 0) {
const uint32_t vn = (bits(machInst, 19, 16) << 1) |
bits(machInst, 7);
- const IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
if (bits(machInst, 20) == 1) {
- return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
+ return new VmovRegCoreW(machInst, rt, (RegIndex)vn);
} else {
- return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
+ return new VmovCoreRegW(machInst, (RegIndex)vn, rt);
}
} else if (a == 0x7) {
- const IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
uint32_t reg = bits(machInst, 19, 16);
uint32_t specReg;
switch (reg) {
@@ -2439,11 +2439,11 @@
return new Unknown(machInst);
}
if (specReg == MISCREG_FPSCR) {
- return new VmsrFpscr(machInst, (IntRegIndex)specReg, rt);
+ return new VmsrFpscr(machInst, (RegIndex)specReg, rt);
} else {
uint32_t iss = mcrMrcIssBuild(0, bits(machInst, 3, 0), rt,
reg, a, bits(machInst, 7, 5));
- return new Vmsr(machInst, (IntRegIndex)specReg, rt, iss);
+ return new Vmsr(machInst, (RegIndex)specReg, rt, iss);
}
}
} else if (l == 0 && c == 1) {
@@ -2452,25 +2452,25 @@
(bits(machInst, 19, 16) << 1);
// Handle accessing each single precision half of the vector.
vd += bits(machInst, 21);
- const IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
if (bits(machInst, 22) == 1) {
- return new VmovCoreRegB(machInst, (IntRegIndex)vd,
+ return new VmovCoreRegB(machInst, (RegIndex)vd,
rt, bits(machInst, 6, 5));
} else if (bits(machInst, 5) == 1) {
- return new VmovCoreRegH(machInst, (IntRegIndex)vd,
+ return new VmovCoreRegH(machInst, (RegIndex)vd,
rt, bits(machInst, 6));
} else if (bits(machInst, 6) == 0) {
- return new VmovCoreRegW(machInst, (IntRegIndex)vd, rt);
+ return new VmovCoreRegW(machInst, (RegIndex)vd, rt);
} else {
return new Unknown(machInst);
}
} else if (bits(q, 1) == 0) {
bool q = bits(machInst, 21);
unsigned be = (bits(machInst, 22) << 1) | (bits(machInst, 5));
- IntRegIndex vd = (IntRegIndex)(2 * (uint32_t)
+ RegIndex vd = (RegIndex)(2 * (uint32_t)
(bits(machInst, 19, 16) | (bits(machInst, 7) << 4)));
- IntRegIndex rt = (IntRegIndex)(uint32_t)
+ RegIndex rt = (RegIndex)(uint32_t)
bits(machInst, 15, 12);
if (q) {
switch (be) {
@@ -2500,16 +2500,16 @@
if (a == 0) {
const uint32_t vn = (bits(machInst, 19, 16) << 1) |
bits(machInst, 7);
- const IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
if (bits(machInst, 20) == 1) {
- return new VmovRegCoreW(machInst, rt, (IntRegIndex)vn);
+ return new VmovRegCoreW(machInst, rt, (RegIndex)vn);
} else {
- return new VmovCoreRegW(machInst, (IntRegIndex)vn, rt);
+ return new VmovCoreRegW(machInst, (RegIndex)vn, rt);
}
} else if (a == 7) {
- const IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
uint32_t reg = bits(machInst, 19, 16);
uint32_t specReg;
switch (reg) {
@@ -2538,11 +2538,11 @@
return new Unknown(machInst);
}
} else if (specReg == MISCREG_FPSCR) {
- return new VmrsFpscr(machInst, rt, (IntRegIndex)specReg);
+ return new VmrsFpscr(machInst, rt, (RegIndex)specReg);
} else {
uint32_t iss = mcrMrcIssBuild(l, bits(machInst, 3, 0), rt,
reg, a, bits(machInst, 7, 5));
- return new Vmrs(machInst, rt, (IntRegIndex)specReg, iss);
+ return new Vmrs(machInst, rt, (RegIndex)specReg, iss);
}
}
} else {
@@ -2551,29 +2551,29 @@
// Handle indexing into each single precision half of the vector.
vd += bits(machInst, 21);
uint32_t index;
- const IntRegIndex rt =
- (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt =
+ (RegIndex)(uint32_t)bits(machInst, 15, 12);
const bool u = (bits(machInst, 23) == 1);
if (bits(machInst, 22) == 1) {
index = bits(machInst, 6, 5);
if (u) {
return new VmovRegCoreUB(machInst, rt,
- (IntRegIndex)vd, index);
+ (RegIndex)vd, index);
} else {
return new VmovRegCoreSB(machInst, rt,
- (IntRegIndex)vd, index);
+ (RegIndex)vd, index);
}
} else if (bits(machInst, 5) == 1) {
index = bits(machInst, 6);
if (u) {
return new VmovRegCoreUH(machInst, rt,
- (IntRegIndex)vd, index);
+ (RegIndex)vd, index);
} else {
return new VmovRegCoreSH(machInst, rt,
- (IntRegIndex)vd, index);
+ (RegIndex)vd, index);
}
} else if (bits(machInst, 6) == 0 && !u) {
- return new VmovRegCoreW(machInst, rt, (IntRegIndex)vd);
+ return new VmovRegCoreW(machInst, rt, (RegIndex)vd);
} else {
return new Unknown(machInst);
}
@@ -2605,22 +2605,22 @@
const bool single = (bits(machInst, 8) == 0);
// Used to select between vcmp and vcmpe.
const bool e = (bits(machInst, 7) == 1);
- IntRegIndex vd;
- IntRegIndex vm;
- IntRegIndex vn;
+ RegIndex vd;
+ RegIndex vm;
+ RegIndex vn;
if (single) {
- vd = (IntRegIndex)(bits(machInst, 22) |
+ vd = (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
- vm = (IntRegIndex)(bits(machInst, 5) |
+ vm = (RegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
- vn = (IntRegIndex)(bits(machInst, 7) |
+ vn = (RegIndex)(bits(machInst, 7) |
(bits(machInst, 19, 16) << 1));
} else {
- vd = (IntRegIndex)((bits(machInst, 22) << 5) |
+ vd = (RegIndex)((bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1));
- vm = (IntRegIndex)((bits(machInst, 5) << 5) |
+ vm = (RegIndex)((bits(machInst, 5) << 5) |
(bits(machInst, 3, 0) << 1));
- vn = (IntRegIndex)((bits(machInst, 7) << 5) |
+ vn = (RegIndex)((bits(machInst, 7) << 5) |
(bits(machInst, 19, 16) << 1));
}
switch (opc1 & 0xb /* 1011 */) {
@@ -2863,11 +2863,11 @@
case 0x7:
if (opc3 == 0x3) {
if (single) {
- vd = (IntRegIndex)((bits(machInst, 22) << 5) |
+ vd = (RegIndex)((bits(machInst, 22) << 5) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpSFpD(machInst, vd, vm);
} else {
- vd = (IntRegIndex)(bits(machInst, 22) |
+ vd = (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpDFpS(machInst, vd, vm);
}
@@ -2878,7 +2878,7 @@
if (single) {
return new VcvtUIntFpS(machInst, vd, vm);
} else {
- vm = (IntRegIndex)(bits(machInst, 5) |
+ vm = (RegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
return new VcvtUIntFpD(machInst, vd, vm);
}
@@ -2886,7 +2886,7 @@
if (single) {
return new VcvtSIntFpS(machInst, vd, vm);
} else {
- vm = (IntRegIndex)(bits(machInst, 5) |
+ vm = (RegIndex)(bits(machInst, 5) |
(bits(machInst, 3, 0) << 1));
return new VcvtSIntFpD(machInst, vd, vm);
}
@@ -2894,7 +2894,7 @@
case 0x9:
if (bits(machInst, 31, 28) != 0xF
&& bits(machInst, 27, 23) == 0x1D) {
- vd = (IntRegIndex)(bits(machInst, 22) |
+ vd = (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VjcvtSFixedFpD(machInst, vd, vm);
}
@@ -2946,7 +2946,7 @@
if (single) {
return new VcvtFpUIntSR(machInst, vd, vm);
} else {
- vd = (IntRegIndex)(bits(machInst, 22) |
+ vd = (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpUIntDR(machInst, vd, vm);
}
@@ -2954,7 +2954,7 @@
if (single) {
return new VcvtFpUIntS(machInst, vd, vm);
} else {
- vd = (IntRegIndex)(bits(machInst, 22) |
+ vd = (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpUIntD(machInst, vd, vm);
}
@@ -2964,7 +2964,7 @@
if (single) {
return new VcvtFpSIntSR(machInst, vd, vm);
} else {
- vd = (IntRegIndex)(bits(machInst, 22) |
+ vd = (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpSIntDR(machInst, vd, vm);
}
@@ -2972,7 +2972,7 @@
if (single) {
return new VcvtFpSIntS(machInst, vd, vm);
} else {
- vd = (IntRegIndex)(bits(machInst, 22) |
+ vd = (RegIndex)(bits(machInst, 22) |
(bits(machInst, 15, 12) << 1));
return new VcvtFpSIntD(machInst, vd, vm);
}
diff --git a/src/arch/arm/isa/formats/macromem.isa b/src/arch/arm/isa/formats/macromem.isa
index 8eb77e9..350908a 100644
--- a/src/arch/arm/isa/formats/macromem.isa
+++ b/src/arch/arm/isa/formats/macromem.isa
@@ -37,7 +37,7 @@
def format ArmMacroMem() {{
decode_block = '''
- return new LdmStm(machInst, (IntRegIndex)(uint32_t)RN, !PREPOST, UP,
+ return new LdmStm(machInst, (RegIndex)(uint32_t)RN, !PREPOST, UP,
PSRUSER, WRITEBACK, LOADOP, machInst.regList);
'''
}};
@@ -45,7 +45,7 @@
def format Thumb16MacroMem() {{
decode_block = '''
{
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 10, 8);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 10, 8);
const bool load = (bits(machInst, 11) == 1);
const uint32_t regList = bits(machInst, 7, 0);
const bool writeback = (!load || bits(regList, rn) == 0);
diff --git a/src/arch/arm/isa/formats/mem.isa b/src/arch/arm/isa/formats/mem.isa
index 7976902..aecd378 100644
--- a/src/arch/arm/isa/formats/mem.isa
+++ b/src/arch/arm/isa/formats/mem.isa
@@ -220,9 +220,9 @@
def format ArmSyncMem() {{
decode_block = '''
{
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt2 = (RegIndex)(uint32_t)bits(machInst, 3, 0);
const auto type_L = bits(machInst, 22, 20);
const auto ex_ord = bits(machInst, 9, 8);
@@ -312,8 +312,8 @@
const bool add = (bits(machInst, 24, 23) == 0x3);
if (bits(machInst, 20) == 1) {
// post == add
- const IntRegIndex rn =
- (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rn =
+ (RegIndex)(uint32_t)bits(machInst, 19, 16);
if (!add && !wb) {
return new %(rfe)s(machInst, rn, RfeOp::DecrementBefore, wb);
} else if (add && !wb) {
@@ -365,10 +365,10 @@
const uint32_t op1 = bits(machInst, 24, 23);
const uint32_t op2 = bits(machInst, 21, 20);
const uint32_t op3 = bits(machInst, 7, 4);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rt2 = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt2 = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t imm8 = bits(machInst, 7, 0);
if (bits(op1, 1) == 0 && bits(op2, 1) == 0) {
if (op1 == 0) {
@@ -525,10 +525,10 @@
uint32_t op2 = bits(machInst, 11, 6);
if (HTRN == 0xF) {
if (UP) {
- return new %(literal_u)s(machInst, RT, INTREG_PC,
+ return new %(literal_u)s(machInst, RT, int_reg::Pc,
true, IMMED_11_0);
} else {
- return new %(literal)s(machInst, RT, INTREG_PC,
+ return new %(literal)s(machInst, RT, int_reg::Pc,
false, IMMED_11_0);
}
} else if (op1 == 0x1) {
@@ -683,9 +683,9 @@
{
const uint32_t op1 = bits(machInst, 24, 23);
const uint32_t op2 = bits(machInst, 11, 6);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t imm12 = bits(machInst, 11, 0);
const uint32_t imm8 = bits(machInst, 7, 0);
bool pldw = bits(machInst, 21);
@@ -695,36 +695,36 @@
const bool add = bits(machInst, 23);
if (bits(op1, 1) == 1) {
if (add) {
- return new %(pli_iulit)s(machInst, INTREG_ZERO,
- INTREG_PC, true, imm12);
+ return new %(pli_iulit)s(machInst, int_reg::Zero,
+ int_reg::Pc, true, imm12);
} else {
- return new %(pli_ilit)s(machInst, INTREG_ZERO,
- INTREG_PC, false, imm12);
+ return new %(pli_ilit)s(machInst, int_reg::Zero,
+ int_reg::Pc, false, imm12);
}
} else {
if (add) {
- return new %(pld_iulit)s(machInst, INTREG_ZERO,
- INTREG_PC, true, imm12);
+ return new %(pld_iulit)s(machInst, int_reg::Zero,
+ int_reg::Pc, true, imm12);
} else {
- return new %(pld_ilit)s(machInst, INTREG_ZERO,
- INTREG_PC, false, imm12);
+ return new %(pld_ilit)s(machInst, int_reg::Zero,
+ int_reg::Pc, false, imm12);
}
}
} else {
if (bits(op1, 1) == 1) {
if (bits(machInst, 23)) {
- return new %(ldrsb_lit_u)s(machInst, rt, INTREG_PC,
+ return new %(ldrsb_lit_u)s(machInst, rt, int_reg::Pc,
true, imm12);
} else {
- return new %(ldrsb_lit)s(machInst, rt, INTREG_PC,
+ return new %(ldrsb_lit)s(machInst, rt, int_reg::Pc,
false, imm12);
}
} else {
if (bits(machInst, 23)) {
- return new %(ldrb_lit_u)s(machInst, rt, INTREG_PC,
+ return new %(ldrb_lit_u)s(machInst, rt, int_reg::Pc,
true, imm12);
} else {
- return new %(ldrb_lit)s(machInst, rt, INTREG_PC,
+ return new %(ldrb_lit)s(machInst, rt, int_reg::Pc,
false, imm12);
}
}
@@ -734,42 +734,42 @@
case 0x0:
if (op2 == 0x0) {
if (pldw) {
- return new %(pldw_radd)s(machInst, INTREG_ZERO,
+ return new %(pldw_radd)s(machInst, int_reg::Zero,
rn, true, imm2, LSL, rm);
} else {
- return new %(pld_radd)s(machInst, INTREG_ZERO,
+ return new %(pld_radd)s(machInst, int_reg::Zero,
rn, true, imm2, LSL, rm);
}
} else if (bits(op2, 5, 2) == 0xc) {
if (pldw) {
- return new %(pldw_isub)s(machInst, INTREG_ZERO,
+ return new %(pldw_isub)s(machInst, int_reg::Zero,
rn, false, imm8);
} else {
- return new %(pld_isub)s(machInst, INTREG_ZERO,
+ return new %(pld_isub)s(machInst, int_reg::Zero,
rn, false, imm8);
}
}
break;
case 0x1:
if (pldw) {
- return new %(pldw_iadd)s(machInst, INTREG_ZERO,
+ return new %(pldw_iadd)s(machInst, int_reg::Zero,
rn, true, imm12);
} else {
- return new %(pld_iadd)s(machInst, INTREG_ZERO,
+ return new %(pld_iadd)s(machInst, int_reg::Zero,
rn, true, imm12);
}
case 0x2:
if (op2 == 0x0) {
- return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
+ return new %(pli_radd)s(machInst, int_reg::Zero, rn,
true, imm2, LSL, rm);
} else if (bits(op2, 5, 2) == 0xc) {
- return new %(pli_ilit)s(machInst, INTREG_ZERO,
- INTREG_PC, false, imm8);
+ return new %(pli_ilit)s(machInst, int_reg::Zero,
+ int_reg::Pc, false, imm8);
}
break;
case 0x3:
- return new %(pli_iulit)s(machInst, INTREG_ZERO,
- INTREG_PC, true, imm12);
+ return new %(pli_iulit)s(machInst, int_reg::Zero,
+ int_reg::Pc, true, imm12);
}
return new Unknown(machInst);
} else {
@@ -880,9 +880,9 @@
{
const uint32_t op1 = bits(machInst, 24, 23);
const uint32_t op2 = bits(machInst, 11, 6);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
const uint32_t imm12 = bits(machInst, 11, 0);
const uint32_t imm8 = bits(machInst, 7, 0);
bool pldw = bits(machInst, 21);
@@ -898,18 +898,18 @@
} else {
if (bits(op1, 1) == 1) {
if (bits(machInst, 23)) {
- return new %(ldrsh_lit_u)s(machInst, rt, INTREG_PC,
+ return new %(ldrsh_lit_u)s(machInst, rt, int_reg::Pc,
true, imm12);
} else {
- return new %(ldrsh_lit)s(machInst, rt, INTREG_PC,
+ return new %(ldrsh_lit)s(machInst, rt, int_reg::Pc,
false, imm12);
}
} else {
if (bits(machInst, 23)) {
- return new %(ldrh_lit_u)s(machInst, rt, INTREG_PC,
+ return new %(ldrh_lit_u)s(machInst, rt, int_reg::Pc,
true, imm12);
} else {
- return new %(ldrh_lit)s(machInst, rt, INTREG_PC,
+ return new %(ldrh_lit)s(machInst, rt, int_reg::Pc,
false, imm12);
}
}
@@ -919,28 +919,28 @@
case 0x0:
if (op2 == 0x0) {
if (pldw) {
- return new %(pldw_radd)s(machInst, INTREG_ZERO,
+ return new %(pldw_radd)s(machInst, int_reg::Zero,
rn, true, imm2, LSL, rm);
} else {
- return new %(pld_radd)s(machInst, INTREG_ZERO,
+ return new %(pld_radd)s(machInst, int_reg::Zero,
rn, true, imm2, LSL, rm);
}
} else if (bits(op2, 5, 2) == 0xc) {
if (pldw) {
- return new %(pldw_isub)s(machInst, INTREG_ZERO,
+ return new %(pldw_isub)s(machInst, int_reg::Zero,
rn, false, imm8);
} else {
- return new %(pld_isub)s(machInst, INTREG_ZERO,
+ return new %(pld_isub)s(machInst, int_reg::Zero,
rn, false, imm8);
}
}
break;
case 0x1:
if (pldw) {
- return new %(pldw_iadd)s(machInst, INTREG_ZERO,
+ return new %(pldw_iadd)s(machInst, int_reg::Zero,
rn, true, imm12);
} else {
- return new %(pld_iadd)s(machInst, INTREG_ZERO,
+ return new %(pld_iadd)s(machInst, int_reg::Zero,
rn, true, imm12);
}
case 0x2:
@@ -1123,9 +1123,11 @@
}
case 0x9:
if (load) {
- return new %(ldr)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
+ return new %(ldr)s(machInst, hrt, int_reg::Sp, true,
+ imm8 << 2);
} else {
- return new %(str)s(machInst, hrt, INTREG_SP, true, imm8 << 2);
+ return new %(str)s(machInst, hrt, int_reg::Sp, true,
+ imm8 << 2);
}
default:
return new Unknown(machInst);
@@ -1148,7 +1150,7 @@
{
const uint32_t rt = bits(machInst, 10, 8);
const uint32_t imm8 = bits(machInst, 7, 0);
- return new %s(machInst, rt, INTREG_PC, true, imm8 << 2);
+ return new %s(machInst, rt, int_reg::Pc, true, imm8 << 2);
}
''' % loadImmClassName(False, True, False)
}};
diff --git a/src/arch/arm/isa/formats/misc.isa b/src/arch/arm/isa/formats/misc.isa
index 1805580..ad3c6e9 100644
--- a/src/arch/arm/isa/formats/misc.isa
+++ b/src/arch/arm/isa/formats/misc.isa
@@ -38,9 +38,9 @@
def format Crc32() {{
decode_block = '''
{
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 15, 12);
uint8_t c_poly = bits(machInst, 9);
uint8_t sz = bits(machInst, 22, 21);
@@ -94,8 +94,8 @@
{
const uint8_t byteMask = bits(machInst, 19, 16);
const uint8_t sysM = byteMask | (bits(machInst, 8) << 4);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 15, 12);
const uint32_t opcode = bits(machInst, 24, 21);
const bool useImm = bits(machInst, 25);
const bool r = bits(machInst, 22);
@@ -159,7 +159,7 @@
const uint32_t opc2 = bits(machInst, 7, 5);
const uint32_t crm = bits(machInst, 3, 0);
const MiscRegIndex miscReg = decodeCP14Reg(crn, opc1, crm, opc2);
- const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 15, 12);
const bool isRead = bits(machInst, 20);
@@ -203,7 +203,7 @@
const uint32_t opc2 = bits(machInst, 7, 5);
const uint32_t crm = bits(machInst, 3, 0);
const MiscRegIndex miscReg = decodeCP15Reg(crn, opc1, crm, opc2);
- const IntRegIndex rt = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rt = (RegIndex)(uint32_t)bits(machInst, 15, 12);
const bool isRead = bits(machInst, 20);
uint32_t iss = mcrMrcIssBuild(isRead, crm, rt, crn, opc1, opc2);
@@ -326,8 +326,8 @@
const uint32_t crm = bits(machInst, 3, 0);
const uint32_t opc1 = bits(machInst, 7, 4);
const MiscRegIndex miscReg = decodeCP15Reg64(crm, opc1);
- const IntRegIndex rt = (IntRegIndex) (uint32_t) bits(machInst, 15, 12);
- const IntRegIndex rt2 = (IntRegIndex) (uint32_t) bits(machInst, 19, 16);
+ const RegIndex rt = (RegIndex) (uint32_t) bits(machInst, 15, 12);
+ const RegIndex rt2 = (RegIndex) (uint32_t) bits(machInst, 19, 16);
const bool isRead = bits(machInst, 20);
diff --git a/src/arch/arm/isa/formats/mult.isa b/src/arch/arm/isa/formats/mult.isa
index dc91da3..3473287 100644
--- a/src/arch/arm/isa/formats/mult.isa
+++ b/src/arch/arm/isa/formats/mult.isa
@@ -40,10 +40,10 @@
// ignored.
const uint32_t op = bits(machInst, 23, 21);
const bool s = bits(machInst, 20);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex ra = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 3, 0);
switch (op) {
case 0x0:
if (s) {
@@ -97,10 +97,10 @@
{
const uint32_t op1 = bits(machInst, 22, 21);
const bool op = bits(machInst, 5);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex ra = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 3, 0);
switch (op1) {
case 0x0:
switch (bits(machInst, 6, 5)) {
@@ -167,10 +167,10 @@
{
const uint32_t op1 = bits(machInst, 22, 20);
const uint32_t op2 = bits(machInst, 5, 4);
- const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex ra = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
if (op1 != 0x1 && bits(op2, 1) != 0) {
return new Unknown(machInst);
}
@@ -292,10 +292,10 @@
{
const uint32_t op1 = bits(machInst, 22, 20);
const uint32_t op2 = bits(machInst, 7, 4);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rdlo = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
- const IntRegIndex rdhi = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rdlo = (RegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rdhi = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 3, 0);
switch (op1) {
case 0x0:
if (op2 == 0x0) {
@@ -368,10 +368,10 @@
// This is 7-5 in the manual, but bit 5 is always ignored.
const uint32_t op2 = bits(machInst, 7, 6);
const bool aIsF = (bits(machInst, 15, 12) == 0xf);
- const IntRegIndex rd = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
- const IntRegIndex rm = (IntRegIndex)(uint32_t)bits(machInst, 11, 8);
- const IntRegIndex ra = (IntRegIndex)(uint32_t)bits(machInst, 15, 12);
+ const RegIndex rd = (RegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rm = (RegIndex)(uint32_t)bits(machInst, 11, 8);
+ const RegIndex ra = (RegIndex)(uint32_t)bits(machInst, 15, 12);
const bool m = bits(machInst, 5);
switch (op1) {
case 0x0:
diff --git a/src/arch/arm/isa/formats/neon64.isa b/src/arch/arm/isa/formats/neon64.isa
index 660d118..72b7e28 100644
--- a/src/arch/arm/isa/formats/neon64.isa
+++ b/src/arch/arm/isa/formats/neon64.isa
@@ -98,9 +98,9 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 15, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t size_q = (size << 1) | q;
uint8_t sz_q = size_q & 0x3;
@@ -513,9 +513,9 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 15, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
switch (opcode) {
case 0x10:
@@ -569,9 +569,9 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 15, 12);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
switch (opcode) {
case 0x0:
@@ -731,8 +731,8 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 16, 12);
- IntRegIndex vd = (IntRegIndex)(uint8_t)bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex)(uint8_t)bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex)(uint8_t)bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex)(uint8_t)bits(machInst, 9, 5);
uint8_t size_q = (size << 1) | q;
uint8_t sz_q = size_q & 0x3;
@@ -1109,8 +1109,8 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 16, 12);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size_q = (size << 1) | q;
uint8_t sz_q = size_q & 0x3;
@@ -1195,8 +1195,8 @@
uint8_t imm5 = bits(machInst, 20, 16);
uint8_t imm4 = bits(machInst, 14, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t imm5_pos = findLsbSet(imm5);
uint8_t index1 = 0, index2 = 0;
@@ -1353,9 +1353,9 @@
uint8_t opcode = bits(machInst, 15, 12);
uint8_t H = bits(machInst, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm_bf = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm_bf = (RegIndex) (uint8_t) bits(machInst, 19, 16);
uint8_t index = 0;
uint8_t index_fp = 0;
@@ -1372,7 +1372,7 @@
index = (H << 1) | L;
vmh = M;
}
- IntRegIndex vm = (IntRegIndex) (uint8_t) (vmh << 4 | vm_bf);
+ RegIndex vm = (RegIndex) (uint8_t) (vmh << 4 | vm_bf);
// Index and 2nd register operand for FP instructions
vmh = M;
@@ -1381,7 +1381,7 @@
} else if (L == 0) {
index_fp = H;
}
- IntRegIndex vm_fp = (IntRegIndex) (uint8_t) (vmh << 4 | vm_bf);
+ RegIndex vm_fp = (RegIndex) (uint8_t) (vmh << 4 | vm_bf);
switch (opcode) {
case 0x0:
@@ -1582,7 +1582,7 @@
uint8_t cmode = bits(machInst, 15, 12);
uint8_t o2 = bits(machInst, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
if (o2 == 0x1 || (op == 0x1 && cmode == 0xf && !q))
return new Unknown64(machInst);
@@ -1698,8 +1698,8 @@
uint8_t immb = bits(machInst, 18, 16);
uint8_t opcode = bits(machInst, 15, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t immh3 = bits(machInst, 22);
uint8_t immh3_q = (immh3 << 1) | q;
@@ -1877,9 +1877,9 @@
{
uint8_t q = bits(machInst, 30);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t switchVal = bits(machInst, 14, 12);
@@ -1938,9 +1938,9 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 14, 12);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
switch (opcode) {
case 0x1:
@@ -1974,9 +1974,9 @@
uint8_t op2 = bits(machInst, 23, 22);
uint8_t imm4 = bits(machInst, 14, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
if (op2 != 0 || (q == 0x0 && bits(imm4, 3) == 0x1))
return new Unknown64(machInst);
@@ -1998,9 +1998,9 @@
uint8_t opcode = bits(machInst, 15, 11);
uint8_t s = bits(machInst, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
switch (opcode) {
case 0x01:
@@ -2142,9 +2142,9 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 15, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
switch (opcode) {
case 0x10:
@@ -2170,9 +2170,9 @@
uint8_t opcode = bits(machInst, 15, 12);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
switch (opcode) {
case 0x9:
@@ -2193,8 +2193,8 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 16, 12);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t switchVal = opcode | ((u ? 1 : 0) << 5);
switch (switchVal) {
@@ -2391,8 +2391,8 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opcode = bits(machInst, 16, 12);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
if (!u) {
if (opcode == 0x1b && size == 0x3)
@@ -2436,8 +2436,8 @@
uint8_t imm5 = bits(machInst, 20, 16);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = findLsbSet(imm5);
if (size > 3)
@@ -2459,9 +2459,9 @@
uint8_t opcode = bits(machInst, 15, 12);
uint8_t H = bits(machInst, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex vm_bf = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vm_bf = (RegIndex) (uint8_t) bits(machInst, 19, 16);
uint8_t index = 0;
uint8_t index_fp = 0;
@@ -2479,7 +2479,7 @@
index = H;
vmh = M;
}
- IntRegIndex vm = (IntRegIndex) (uint8_t) (vmh << 4 | vm_bf);
+ RegIndex vm = (RegIndex) (uint8_t) (vmh << 4 | vm_bf);
// Index and 2nd register operand for FP instructions
vmh = M;
@@ -2488,7 +2488,7 @@
} else if (L == 0) {
index_fp = H;
}
- IntRegIndex vm_fp = (IntRegIndex) (uint8_t) (vmh << 4 | vm_bf);
+ RegIndex vm_fp = (RegIndex) (uint8_t) (vmh << 4 | vm_bf);
uint8_t u_opcode = opcode | u << 4;
@@ -2563,8 +2563,8 @@
uint8_t immb = bits(machInst, 18, 16);
uint8_t opcode = bits(machInst, 15, 11);
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t immh3 = bits(machInst, 22);
uint8_t size = findMsbSet(immh);
@@ -2748,9 +2748,9 @@
return new Unknown64(machInst);
}
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
if (load) {
return new VldMult64(machInst, rn, vd, rm, eSize, dataSize,
@@ -2797,9 +2797,9 @@
uint8_t eSize = scale;
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
if (load) {
return new VldSingle64(machInst, rn, vd, rm, eSize, dataSize,
diff --git a/src/arch/arm/isa/formats/sve_2nd_level.isa b/src/arch/arm/isa/formats/sve_2nd_level.isa
index 53fd80d..cbd5466 100644
--- a/src/arch/arm/isa/formats/sve_2nd_level.isa
+++ b/src/arch/arm/isa/formats/sve_2nd_level.isa
@@ -43,9 +43,9 @@
StaticInstPtr
decodeSveIntArithBinPred(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
switch (bits(machInst, 20, 19)) {
case 0x0:
@@ -147,9 +147,9 @@
StaticInstPtr
decodeSveIntReduc(ExtMachInst machInst)
{
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
@@ -221,10 +221,10 @@
StaticInstPtr
decodeSveIntMulAdd(ExtMachInst machInst)
{
- IntRegIndex zda = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
uint8_t opc = (bits(machInst, 15) << 1) | bits(machInst, 13);
@@ -248,8 +248,8 @@
StaticInstPtr
decodeSveShiftByImmPred0(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t imm3 = (uint8_t) bits(machInst, 7, 5);
uint8_t tsize = (bits(machInst, 23, 22) << 2) | bits(machInst, 9, 8);
@@ -304,9 +304,9 @@
StaticInstPtr
decodeSveShiftByVectorPred(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
uint8_t opc = bits(machInst, 18, 16);
switch (opc) {
@@ -335,9 +335,9 @@
StaticInstPtr
decodeSveShiftByWideElemsPred(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
uint8_t opc = bits(machInst, 18, 16);
switch (opc) {
@@ -373,9 +373,9 @@
StaticInstPtr
decodeSveIntArithUnaryPred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
unsigned esize = bits(machInst, 23, 22);
uint8_t opg = bits(machInst, 20, 19);
uint8_t opc = bits(machInst, 18, 16);
@@ -451,9 +451,9 @@
StaticInstPtr
decodeSveIntArithUnpred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t opc = (uint8_t) bits(machInst, 12, 10);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
@@ -485,9 +485,9 @@
StaticInstPtr
decodeSveIntLogUnpred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t opc = (uint8_t) (bits(machInst, 23, 22) << 3
| bits(machInst, 12, 10));
@@ -508,7 +508,7 @@
StaticInstPtr
decodeSveIndexGen(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
uint8_t grp = (uint8_t) bits(machInst, 11, 10);
@@ -536,7 +536,7 @@
case 1:
{ // INDEX (scalar, immediate)
int8_t imm5 = sext<5>(bits(machInst, 20, 16));
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(
+ RegIndex zn = (RegIndex) (uint8_t) bits(
machInst, 9, 5);
switch (size) {
case 0:
@@ -557,7 +557,7 @@
case 2:
{ // INDEX (immediate, scalar)
int8_t imm5 = sext<5>(bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(
+ RegIndex zm = (RegIndex) (uint8_t) bits(
machInst, 20, 16);
switch (size) {
case 0:
@@ -577,9 +577,9 @@
}
case 3:
{ // INDEX (scalars)
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(
+ RegIndex zn = (RegIndex) (uint8_t) bits(
machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(
+ RegIndex zm = (RegIndex) (uint8_t) bits(
machInst, 20, 16);
switch (size) {
case 0:
@@ -606,10 +606,10 @@
uint8_t b23_22 = bits(machInst, 23, 22);
uint8_t b11 = bits(machInst, 11);
if ((b23_22 & 0x2) == 0x0 && b11 == 0x0) {
- IntRegIndex rd = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 4, 0));
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 20, 16));
+ RegIndex rd = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 4, 0));
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 20, 16));
uint64_t imm = sext<6>(bits(machInst, 10, 5));
if ((b23_22 & 0x1) == 0x0) {
return new AddvlXImm(machInst, rd, rn, imm);
@@ -617,7 +617,7 @@
return new AddplXImm(machInst, rd, rn, imm);
}
} else if (b23_22 == 0x2 && b11 == 0x0) {
- IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
uint64_t imm = sext<6>(bits(machInst, 10, 5));
if (bits(machInst, 20, 16) == 0x1f) {
return new SveRdvl(machInst, rd, imm);
@@ -629,9 +629,9 @@
StaticInstPtr
decodeSveShiftByWideElemsUnpred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t size = bits(machInst, 23, 22);
uint8_t opc = (uint8_t) bits(machInst, 11, 10);
switch (opc) {
@@ -651,8 +651,8 @@
StaticInstPtr
decodeSveShiftByImmUnpredB(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t imm3 = (uint8_t) bits(machInst, 18, 16);
uint8_t tsize = (bits(machInst, 23, 22) << 2) | bits(machInst, 20, 19);
@@ -712,9 +712,9 @@
StaticInstPtr
decodeSveCompVecAddr(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t mult = 1 << bits(machInst, 11, 10);
uint8_t opc = bits(machInst, 23, 22);
@@ -739,8 +739,8 @@
StaticInstPtr
decodeSveIntMiscUnpred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = bits(machInst, 23, 22);
uint8_t opc = bits(machInst, 11, 10);
@@ -751,7 +751,7 @@
if (size == 0) {
break;
}
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst,
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst,
20, 16);
return decodeSveBinUnpredF<SveFtssel>(
size, machInst, zd, zn, zm);
@@ -783,7 +783,7 @@
if (b13_12 == 0) {
uint8_t pattern = (uint8_t) bits(machInst, 9, 5);
uint8_t imm4 = (uint8_t) bits(machInst, 19, 16) + 1;
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
unsigned size = (unsigned) bits(machInst, 23, 22);
if (opc20) {
if (opc11 == 0) {
@@ -817,7 +817,7 @@
} else if (b13_12 == 3) {
uint8_t pattern = (uint8_t) bits(machInst, 9, 5);
uint8_t imm4 = (uint8_t) bits(machInst, 19, 16) + 1;
- IntRegIndex rdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
unsigned size = (unsigned) bits(machInst, 23, 22);
switch (opc11_10) {
case 0:
@@ -856,7 +856,7 @@
} else if (opc20 && b13_12 == 2 && !(opc11_10 & 0x2)) {
uint8_t pattern = (uint8_t) bits(machInst, 9, 5);
uint8_t imm4 = (uint8_t) bits(machInst, 19, 16) + 1;
- IntRegIndex rdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
unsigned size = (unsigned) bits(machInst, 23, 22);
if (opc11_10 & 0x1) {
return decodeSveElemIntCountU<SveDec>(size, machInst,
@@ -868,7 +868,7 @@
} else if (!opc20 && b13_12 == 2 && opc11_10 == 0) {
uint8_t pattern = (uint8_t) bits(machInst, 9, 5);
uint8_t imm4 = (uint8_t) bits(machInst, 19, 16) + 1;
- IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
unsigned size = (unsigned) bits(machInst, 23, 22);
return decodeSveElemIntCountU<SveCntx>(size, machInst,
rd, pattern, imm4);
@@ -879,7 +879,7 @@
StaticInstPtr
decodeSveLogMaskImm(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
bool n = bits(machInst, 17);
uint8_t immr = bits(machInst, 16, 11);
uint8_t imms = bits(machInst, 10, 5);
@@ -932,8 +932,8 @@
StaticInstPtr
decodeSveIntWideImmPred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 19, 16);
uint8_t size = bits(machInst, 23, 22);
if (bits(machInst, 15) == 0x0) {
@@ -982,8 +982,8 @@
if (!b23_22) {
uint8_t position =
bits(machInst, 20, 16) << 3 | bits(machInst, 12, 10);
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
return new SveExt<uint8_t>(machInst, zdn, zm, position);
}
return new Unknown64(machInst);
@@ -995,38 +995,38 @@
uint8_t b12_10 = bits(machInst, 12, 10);
if (b12_10 == 0x4) {
unsigned size = (unsigned) bits(machInst, 23, 22);
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
return decodeSveBinUnpredU<SveTbl>(size, machInst, zd, zn, zm);
} else if (bits(machInst, 20, 16) == 0x0 && b12_10 == 0x6) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
return decodeSveUnaryUnpredU<SveDupScalar>(size, machInst, zd, rn);
} else if (bits(machInst, 20, 16) == 0x4 && b12_10 == 0x6) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
return decodeSveUnaryUnpredU<SveInsr>(size, machInst, zdn, rm);
} else if (bits(machInst, 20, 16) == 0x14 && b12_10 == 0x6) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex vm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex vm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
return decodeSveUnaryUnpredU<SveInsrf>(size, machInst, zdn, vm);
} else if (bits(machInst, 20, 16) == 0x18 && b12_10 == 0x6) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
return decodeSveUnaryUnpredU<SveRevv>(size, machInst, zd, zn);
} else if (b12_10 == 0x0 && bits(machInst, 20, 16) != 0x0) {
uint8_t imm =
bits(machInst, 23, 22) << 5 | // imm3h
bits(machInst, 20) << 4 | // imm3l
bits(machInst, 19, 16); // tsz
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
if (imm & 0x1) {
imm >>= 1;
return new SveDupIdx<uint8_t>(machInst, zd, zn, imm);
@@ -1047,8 +1047,8 @@
} else if (bits(machInst, 23, 22) != 0x0 &&
bits(machInst, 20, 18) == 0x4 && b12_10 == 0x6) {
unsigned size = (unsigned) bits(machInst, 23, 22);
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
if (bits(machInst, 17)) {
if (bits(machInst, 16)) {
return decodeSveUnpackU<SveUunpkhi>(size, machInst,
@@ -1075,9 +1075,9 @@
{
if (bits(machInst, 20) == 0x0 && bits(machInst, 12, 11) != 0x3 &&
bits(machInst, 9) == 0x0 && bits(machInst, 4) == 0x0) {
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t size = bits(machInst, 23, 22);
@@ -1106,8 +1106,8 @@
} else if (bits(machInst, 23, 22) == 0x0 &&
bits(machInst, 20, 17) == 0x8 && bits(machInst, 12, 9) == 0x0
&& bits(machInst, 4) == 0x0) {
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex pn = (IntRegIndex) (uint8_t) bits(machInst, 8, 5);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex pn = (RegIndex) (uint8_t) bits(machInst, 8, 5);
if (bits(machInst, 16)) {
return new SvePunpkhi<uint8_t, uint16_t>(machInst, pd, pn);
} else {
@@ -1116,8 +1116,8 @@
} else if (bits(machInst, 20, 16) == 0x14 &&
bits(machInst, 12, 9) == 0x00 && bits(machInst, 4) == 0) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex pn = (IntRegIndex) (uint8_t) bits(machInst, 8, 5);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex pn = (RegIndex) (uint8_t) bits(machInst, 8, 5);
return decodeSveUnaryUnpredU<SveRevp>(size, machInst, pd, pn);
}
return new Unknown64(machInst);
@@ -1126,9 +1126,9 @@
StaticInstPtr
decodeSvePermIntlv(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t size = bits(machInst, 23, 22);
@@ -1160,9 +1160,9 @@
case 0x0:
if (!b13) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex vn = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex zd = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex vn = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex)(uint8_t) bits(machInst, 4, 0);
return decodeSveUnaryPredU<SveCpySimdFpScalar>(size,
machInst, zd, vn, pg);
}
@@ -1170,9 +1170,9 @@
case 0x1:
if (!b13 && b23) {
// sve_int_perm_compact
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zn = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex zd = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zn = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex)(uint8_t) bits(machInst, 4, 0);
if (bits(machInst, 22)) {
return new SveCompact<uint64_t>(machInst, zd, zn, pg);
} else {
@@ -1183,10 +1183,10 @@
case 0x8:
if (b13) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex rn = makeSP(
- (IntRegIndex)(uint8_t) bits(machInst, 9, 5));
- IntRegIndex zd = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex rn = makeSP(
+ (RegIndex)(uint8_t) bits(machInst, 9, 5));
+ RegIndex zd = (RegIndex)(uint8_t) bits(machInst, 4, 0);
return decodeSveUnaryPredU<SveCpyScalar>(size,
machInst, zd, rn, pg);
}
@@ -1194,9 +1194,9 @@
case 0xC:
if (!b13) {
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zdn = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex)(uint8_t) bits(machInst, 9, 5);
return decodeSveBinDestrPredU<SveSplice>(size, machInst,
zdn, zm, pg);
}
@@ -1207,9 +1207,9 @@
if (b13) {
uint8_t AB = bits(machInst, 16);
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zn = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex rd = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zn = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex rd = (RegIndex)(uint8_t) bits(machInst, 4, 0);
if (!AB) {
return decodeSveUnaryPredU<SveLasta>(size,
machInst, rd, zn, pg);
@@ -1223,9 +1223,9 @@
if (!b13) {
uint8_t AB = bits(machInst, 16);
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zn = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex vd = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zn = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex vd = (RegIndex)(uint8_t) bits(machInst, 4, 0);
if (!AB) {
return decodeSveUnaryPredU<SveLastaf>(size,
machInst, vd, zn, pg);
@@ -1239,9 +1239,9 @@
if (!b13) {
uint8_t AB = bits(machInst, 16);
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zm = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex zdn = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zm = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex zdn = (RegIndex)(uint8_t) bits(machInst, 4, 0);
if (!AB) {
return decodeSveUnaryPredU<SveClastav>(size,
machInst, zdn, zm, pg);
@@ -1255,9 +1255,9 @@
if (!b13) {
uint8_t AB = bits(machInst, 16);
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zm = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex zdn = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zm = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex zdn = (RegIndex)(uint8_t) bits(machInst, 4, 0);
if (!AB) {
return decodeSveUnaryPredU<SveClastaf>(size,
machInst, zdn, zm, pg);
@@ -1271,9 +1271,9 @@
if (b13) {
uint8_t AB = bits(machInst, 16);
uint8_t size = bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zm = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex rdn = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zm = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex rdn = (RegIndex)(uint8_t) bits(machInst, 4, 0);
if (!AB) {
return decodeSveUnaryPredU<SveClasta>(size,
machInst, rdn, zm, pg);
@@ -1286,9 +1286,9 @@
}
if (bits(machInst, 20, 18) == 0x1 && !b13) {
unsigned size = (unsigned) bits(machInst, 23, 22);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex zn = (IntRegIndex)(uint8_t) bits(machInst, 9, 5);
- IntRegIndex zd = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zn = (RegIndex)(uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex)(uint8_t) bits(machInst, 4, 0);
uint8_t opc17_16 = bits(machInst, 17, 16);
switch (opc17_16) {
case 0x00:
@@ -1325,10 +1325,10 @@
StaticInstPtr
decodeSveSelVec(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 13, 10);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 13, 10);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t size = bits(machInst, 23, 22);
@@ -1345,10 +1345,10 @@
bits(machInst, 15) << 2 |
bits(machInst, 13) << 1 |
bits(machInst, 4);
- IntRegIndex pd = (IntRegIndex) (uint8_t)bits(machInst, 3, 0);
- IntRegIndex pg = (IntRegIndex) (uint8_t)bits(machInst, 12, 10);
- IntRegIndex zn = (IntRegIndex) (uint8_t)bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t)bits(machInst, 20, 16);
+ RegIndex pd = (RegIndex) (uint8_t)bits(machInst, 3, 0);
+ RegIndex pg = (RegIndex) (uint8_t)bits(machInst, 12, 10);
+ RegIndex zn = (RegIndex) (uint8_t)bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t)bits(machInst, 20, 16);
if (b14 && size != 3) {
// sve_int_cmp_1
switch (opc) {
@@ -1418,9 +1418,9 @@
decodeSveIntCmpUImm(ExtMachInst machInst)
{
uint8_t cmp = bits(machInst, 13) << 1 | bits(machInst, 4);
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
int64_t imm = (int64_t) bits(machInst, 20, 14);
uint8_t size = bits(machInst, 23, 22);
switch (cmp) {
@@ -1445,9 +1445,9 @@
{
uint8_t opc = bits(machInst, 15) << 2 | bits(machInst, 13) << 1 |
bits(machInst, 4);
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
int64_t imm = sext<5>(bits(machInst, 20, 16));
uint8_t size = bits(machInst, 23, 22);
switch (opc) {
@@ -1478,10 +1478,10 @@
StaticInstPtr
decodeSvePredLogicalOps(ExtMachInst machInst)
{
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex pn = (IntRegIndex) (uint8_t) bits(machInst, 8, 5);
- IntRegIndex pm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 13, 10);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex pn = (RegIndex) (uint8_t) bits(machInst, 8, 5);
+ RegIndex pm = (RegIndex) (uint8_t) bits(machInst, 19, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 13, 10);
uint8_t opc = (bits(machInst, 23, 22) << 2) |
(bits(machInst, 9) << 1) |
bits(machInst, 4);
@@ -1526,10 +1526,10 @@
{
if (bits(machInst, 23) == 0x0 && bits(machInst, 9) == 0x0) {
uint8_t opc = (bits(machInst, 22) << 1) | bits(machInst, 4);
- IntRegIndex pm = (IntRegIndex)(uint8_t) bits(machInst, 19, 16);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 13, 10);
- IntRegIndex pn = (IntRegIndex)(uint8_t) bits(machInst, 8, 5);
- IntRegIndex pd = (IntRegIndex)(uint8_t) bits(machInst, 3, 0);
+ RegIndex pm = (RegIndex)(uint8_t) bits(machInst, 19, 16);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 13, 10);
+ RegIndex pn = (RegIndex)(uint8_t) bits(machInst, 8, 5);
+ RegIndex pd = (RegIndex)(uint8_t) bits(machInst, 3, 0);
switch (opc) {
case 0x0:
// BRKPA
@@ -1554,9 +1554,9 @@
if (bits(machInst, 18, 16) == 0x0 && bits(machInst, 9) == 0x0) {
bool flagset = bits(machInst, 22);
bool merging = bits(machInst, 4);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 13, 10);
- IntRegIndex pn = (IntRegIndex)(uint8_t) bits(machInst, 8, 5);
- IntRegIndex pd = (IntRegIndex)(uint8_t) bits(machInst, 3, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 13, 10);
+ RegIndex pn = (RegIndex)(uint8_t) bits(machInst, 8, 5);
+ RegIndex pd = (RegIndex)(uint8_t) bits(machInst, 3, 0);
if (bits(machInst, 23)) {
if (flagset) {
if (!merging) {
@@ -1593,8 +1593,8 @@
if (bits(machInst, 23, 22) == 0x1 &&
bits(machInst, 18, 16) == 0x0 &&
bits(machInst, 9) == 0x0) {
- IntRegIndex pn = (IntRegIndex) (uint8_t) bits(machInst, 8, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 13, 10);
+ RegIndex pn = (RegIndex) (uint8_t) bits(machInst, 8, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 13, 10);
return new SvePtest(machInst, pn, pg);
}
return new Unknown64(machInst);
@@ -1606,8 +1606,8 @@
uint8_t size = bits(machInst, 23, 22);
uint8_t opc18_16 = bits(machInst, 18, 16);
uint8_t opc10_9 = bits(machInst, 10, 9);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 8, 5);
- IntRegIndex pdn = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 8, 5);
+ RegIndex pdn = (RegIndex) (uint8_t) bits(machInst, 3, 0);
if (opc18_16 == 0x1 && opc10_9 == 0x2) {
return decodeSveUnaryPredU<SvePnext>(size,
machInst, pdn, pdn, pg);
@@ -1620,7 +1620,7 @@
StaticInstPtr
decodeSveInitPred(ExtMachInst machInst)
{
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
unsigned size = bits(machInst, 23, 22);
uint8_t imm = bits(machInst, 9, 5);
@@ -1636,7 +1636,7 @@
decodeSveZeroPredReg(ExtMachInst machInst)
{
if (bits(machInst, 23, 22) == 0x0 && bits(machInst, 18, 16) == 0x0) {
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
return new SvePfalse(machInst, pd);
}
return new Unknown64(machInst);
@@ -1649,9 +1649,9 @@
bits(machInst, 18, 16) == 0x0 &&
bits(machInst, 9) == 0x0 &&
bits(machInst, 4) == 0x0) {
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 13, 10);
- IntRegIndex pn = (IntRegIndex)(uint8_t) bits(machInst, 8, 5);
- IntRegIndex pdm = (IntRegIndex)(uint8_t) bits(machInst, 3, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 13, 10);
+ RegIndex pn = (RegIndex)(uint8_t) bits(machInst, 8, 5);
+ RegIndex pdm = (RegIndex)(uint8_t) bits(machInst, 3, 0);
if (bits(machInst, 22) == 0x0) {
return new SveBrkn(machInst, pdm, pn, pdm, pg);
} else {
@@ -1668,8 +1668,8 @@
if (bits(machInst, 23)) {
return new Unknown64(machInst);
}
- IntRegIndex pd = (IntRegIndex)(uint8_t) bits(machInst, 3, 0);
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 8, 5);
+ RegIndex pd = (RegIndex)(uint8_t) bits(machInst, 3, 0);
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 8, 5);
if (bits(machInst, 22)) {
return new SveRdffrsPred(machInst, pd, pg);
} else {
@@ -1683,7 +1683,7 @@
if (bits(machInst, 23, 22) != 0) {
return new Unknown64(machInst);
}
- IntRegIndex pd = (IntRegIndex)(uint8_t) bits(machInst, 3, 0);
+ RegIndex pd = (RegIndex)(uint8_t) bits(machInst, 3, 0);
return new SveRdffrUnpred(machInst, pd);
} // decodeSveReadPredFromFFRUnpred
@@ -1756,9 +1756,9 @@
if (bits(machInst, 10, 9) != 0x0) {
return new Unknown64(machInst);
}
- IntRegIndex zdn = (IntRegIndex) (uint8_t)
+ RegIndex zdn = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 8, 5);
uint8_t esize = bits(machInst, 23, 22);
if (esize == 0x0) {
@@ -1797,9 +1797,9 @@
break;
case 0x1:
{
- IntRegIndex rdn = (IntRegIndex) (uint8_t)
+ RegIndex rdn = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 8, 5);
uint8_t esize = bits(machInst, 23, 22);
uint8_t opc = bits(machInst, 18, 17);
@@ -1861,7 +1861,7 @@
bits(machInst, 4, 0) == 0x0) {
uint8_t opc = bits(machInst, 18, 16);
if (opc == 0x0) {
- IntRegIndex pn = (IntRegIndex)(uint8_t)
+ RegIndex pn = (RegIndex)(uint8_t)
bits(machInst, 8, 5);
return new SveWrffr(machInst, pn);
} else if (opc == 0x4 && bits(machInst, 8, 5) == 0x0) {
@@ -1873,9 +1873,9 @@
} else {
uint8_t opc = bits(machInst, 18, 16);
if (opc == 0 && bits(machInst, 9) == 0) {
- IntRegIndex rd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex pn = (IntRegIndex) (uint8_t) bits(machInst, 8, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 13,
+ RegIndex rd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex pn = (RegIndex) (uint8_t) bits(machInst, 8, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 13,
10);
uint8_t esize = bits(machInst, 23, 22);
return decodeSveUnaryPredU<SveCntp>(esize,
@@ -1892,8 +1892,8 @@
(bits(machInst, 23) << 8) | (bits(machInst, 13, 10) << 4) |
bits(machInst, 3, 0);
uint8_t b10 = (uint8_t) bits(machInst, 10);
- IntRegIndex rn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex rn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
if (b23_13_12_11_10_3_2_1_0 == 0x180) {
uint8_t s64b = bits(machInst, 22);
uint8_t ne = bits(machInst, 4);
@@ -1911,7 +1911,7 @@
}
}
} else if (b10) {
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
uint8_t s64b = (uint8_t) bits(machInst, 12);
uint8_t opc = (uint8_t) bits(machInst, 11) << 1 |
@@ -1954,7 +1954,7 @@
StaticInstPtr
decodeSveIntWideImmUnpred0(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
uint64_t imm = bits(machInst, 12, 5);
uint8_t sh = bits(machInst, 13);
uint8_t size = bits(machInst, 23, 22);
@@ -1996,7 +1996,7 @@
StaticInstPtr
decodeSveIntWideImmUnpred1(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
uint64_t imm = bits(machInst, 12, 5);
uint8_t size = bits(machInst, 23, 22);
@@ -2021,7 +2021,7 @@
StaticInstPtr
decodeSveIntWideImmUnpred2(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
uint64_t imm = bits(machInst, 12, 5);
uint8_t size = bits(machInst, 23, 22);
@@ -2036,7 +2036,7 @@
StaticInstPtr
decodeSveIntWideImmUnpred3(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
uint64_t imm = bits(machInst, 12, 5);
uint8_t sh = bits(machInst, 13);
uint8_t size = bits(machInst, 23, 22);
@@ -2064,7 +2064,7 @@
StaticInstPtr
decodeSveIntWideImmUnpred4(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
uint8_t size = bits(machInst, 23, 22);
if (bits(machInst, 18, 17) == 0x0 && size != 0x0) {
@@ -2109,9 +2109,9 @@
StaticInstPtr
decodeSveMultiplyAddUnpred(ExtMachInst machInst)
{
- IntRegIndex zda = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
@@ -2144,8 +2144,8 @@
StaticInstPtr
decodeSveMultiplyIndexed(ExtMachInst machInst)
{
- IntRegIndex zda = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
@@ -2155,7 +2155,7 @@
uint8_t usig = (uint8_t) bits(machInst, 10);
if (size & 0x1) {
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 19, 16);
uint8_t i1 = (uint8_t) bits(machInst, 20);
if (usig) {
return new SveUdoti<uint16_t, uint64_t>(machInst,
@@ -2165,7 +2165,7 @@
zda, zn, zm, i1);
}
} else {
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 18, 16);
uint8_t i2 = (uint8_t) bits(machInst, 20, 19);
if (usig) {
return new SveUdoti<uint8_t, uint32_t>(machInst,
@@ -2181,9 +2181,9 @@
StaticInstPtr
decodeSveFpFastReduc(ExtMachInst machInst)
{
- IntRegIndex vd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex vd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
@@ -2210,8 +2210,8 @@
StaticInstPtr
decodeSveFpUnaryUnpred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
if (size == 0) {
@@ -2233,9 +2233,9 @@
StaticInstPtr
decodeSveFpCmpZero(ExtMachInst machInst)
{
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
if (size == 0) {
@@ -2275,9 +2275,9 @@
return new Unknown64(machInst);
}
- IntRegIndex vdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex vdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
return decodeSveUnaryPredF<SveFadda>(size, machInst, vdn, zm, pg);
} // decodeSveFpAccumReduc
@@ -2285,9 +2285,9 @@
StaticInstPtr
decodeSveFpArithUnpred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t size = bits(machInst, 23, 22);
if (size == 0) {
@@ -2321,9 +2321,9 @@
StaticInstPtr
decodeSveFpArithPred0(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
if (size == 0) {
@@ -2378,8 +2378,8 @@
StaticInstPtr
decodeSveFpTrigMAddCoeff(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t imm = (uint8_t) bits(machInst, 18, 16);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
@@ -2393,8 +2393,8 @@
StaticInstPtr
decodeSveFpArithImmPred(ExtMachInst machInst)
{
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint64_t imm;
uint8_t size = (uint8_t) bits(machInst, 23, 22);
@@ -2456,9 +2456,9 @@
StaticInstPtr
decodeSveFpUnaryPred(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = (uint8_t) bits(machInst, 23, 22);
if (size == 0) {
@@ -2656,10 +2656,10 @@
StaticInstPtr
decodeSveFpCmpVec(ExtMachInst machInst)
{
- IntRegIndex pd = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pd = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
if (size == 0) {
@@ -2691,10 +2691,10 @@
StaticInstPtr
decodeSveFpFusedMulAdd(ExtMachInst machInst)
{
- IntRegIndex zda = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t size = bits(machInst, 23, 22);
if (size == 0) {
@@ -2736,9 +2736,9 @@
{
uint8_t size = bits(machInst, 23, 22);
uint8_t rot = bits(machInst, 16) << 1 | 0x01;
- IntRegIndex zdn = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zdn = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
switch (size) {
case 1:
return new SveFcadd<uint16_t>(machInst,
@@ -2761,10 +2761,10 @@
return new Unknown64(machInst);
}
- IntRegIndex zda = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
- IntRegIndex zm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
uint8_t rot = bits(machInst, 14, 13);
switch (size) {
case 1:
@@ -2789,20 +2789,20 @@
return new Unknown64(machInst);
}
- IntRegIndex zda = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
- IntRegIndex zm;
+ RegIndex zda = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zm;
uint8_t rot = bits(machInst, 11, 10);
uint8_t imm;
switch (size) {
case 2:
- zm = (IntRegIndex) (uint8_t) bits(machInst, 18, 16);
+ zm = (RegIndex) (uint8_t) bits(machInst, 18, 16);
imm = bits(machInst, 20, 19);
return new SveFcmlai<uint16_t>(machInst,
zda, zn, zm, rot, imm);
case 3:
- zm = (IntRegIndex) (uint8_t) bits(machInst, 19, 16);
+ zm = (RegIndex) (uint8_t) bits(machInst, 19, 16);
imm = bits(machInst, 20);
return new SveFcmlai<uint32_t>(machInst,
zda, zn, zm, rot, imm);
@@ -2813,8 +2813,8 @@
StaticInstPtr
decodeSveFpMulIndexed(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint8_t size = bits(machInst, 23, 22);
switch (size) {
@@ -2822,17 +2822,17 @@
case 0x1:
return new SveFmulIdx<uint16_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 18, 16),
+ (RegIndex) (uint8_t) bits(machInst, 18, 16),
bits(machInst, 20, 19) | (bits(machInst, 22) << 2));
case 0x2:
return new SveFmulIdx<uint32_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 18, 16),
+ (RegIndex) (uint8_t) bits(machInst, 18, 16),
bits(machInst, 20, 19));
case 0x3:
return new SveFmulIdx<uint64_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 19, 16),
+ (RegIndex) (uint8_t) bits(machInst, 19, 16),
bits(machInst, 20));
default:
return new Unknown64(machInst);
@@ -2843,8 +2843,8 @@
StaticInstPtr
decodeSveFpMulAddIndexed(ExtMachInst machInst)
{
- IntRegIndex zd = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zd = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
const uint8_t op = bits(machInst, 10);
uint8_t size = bits(machInst, 23, 22);
@@ -2854,36 +2854,36 @@
if (op) {
return new SveFmlsIdx<uint16_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 18, 16),
+ (RegIndex) (uint8_t) bits(machInst, 18, 16),
bits(machInst, 20, 19) | (bits(machInst, 22) << 2));
} else {
return new SveFmlaIdx<uint16_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 18, 16),
+ (RegIndex) (uint8_t) bits(machInst, 18, 16),
bits(machInst, 20, 19) | (bits(machInst, 22) << 2));
}
case 0x2:
if (op) {
return new SveFmlsIdx<uint32_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 18, 16),
+ (RegIndex) (uint8_t) bits(machInst, 18, 16),
bits(machInst, 20, 19));
} else {
return new SveFmlaIdx<uint32_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 18, 16),
+ (RegIndex) (uint8_t) bits(machInst, 18, 16),
bits(machInst, 20, 19));
}
case 0x3:
if (op) {
return new SveFmlsIdx<uint64_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 19, 16),
+ (RegIndex) (uint8_t) bits(machInst, 19, 16),
bits(machInst, 20));
} else {
return new SveFmlaIdx<uint64_t>(
machInst, zd, zn,
- (IntRegIndex) (uint8_t) bits(machInst, 19, 16),
+ (RegIndex) (uint8_t) bits(machInst, 19, 16),
bits(machInst, 20));
}
default:
@@ -2897,11 +2897,11 @@
if (bits(machInst, 15)) {
if (bits(machInst, 22)) {
// SVE load and broadcast element
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
uint64_t imm = bits(machInst, 21, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 2) |
bits(machInst, 14, 13);
@@ -2910,12 +2910,12 @@
} else {
if (bits(machInst, 21)) {
// SVE 32-bit gather load (vector plus immediate)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t)
+ RegIndex zn = (RegIndex) (uint8_t)
bits(machInst, 9, 5);
uint64_t imm = bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 1) |
bits(machInst, 14);
@@ -2938,12 +2938,12 @@
uint8_t b24_23 = bits(machInst, 24, 23);
if (b24_23 != 0x3 && bits(machInst, 21) == 0) {
// SVE 32-bit gather load (scalar plus 32-bit unscaled offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 1) |
bits(machInst, 14);
@@ -2964,13 +2964,13 @@
if (bits(machInst, 21)) {
// SVE 32-bit gather load halfwords (scalar plus 32-bit
// scaled offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t xs = bits(machInst, 22);
uint8_t ff = bits(machInst, 13);
@@ -2995,13 +2995,13 @@
if (bits(machInst, 21)) {
// SVE 32-bit gather load words (scalar plus 32-bit scaled
// offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t xs = bits(machInst, 22);
uint8_t ff = bits(machInst, 13);
@@ -3016,20 +3016,20 @@
if (bits(machInst, 22) == 0 && bits(machInst, 14, 13) == 0x0 &&
bits(machInst, 4) == 0) {
// SVE load predicate register
- IntRegIndex pt = (IntRegIndex) (uint8_t)
+ RegIndex pt = (RegIndex) (uint8_t)
bits(machInst, 3, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
bits(machInst, 12, 10));
return new SveLdrPred(machInst, pt, rn, imm);
} else if (bits(machInst, 22) == 0 &&
bits(machInst, 14, 13) == 0x2) {
// SVE load vector register
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
uint64_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
bits(machInst, 12, 10));
return new SveLdrVec(machInst, zt, rn, imm);
@@ -3052,10 +3052,10 @@
return new Unknown64(machInst);
}
- IntRegIndex zt = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex)(uint8_t) bits(machInst, 9, 5));
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
- IntRegIndex rm = (IntRegIndex)(uint8_t) bits(machInst, 20, 16);
+ RegIndex zt = (RegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex)(uint8_t) bits(machInst, 9, 5));
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex rm = (RegIndex)(uint8_t) bits(machInst, 20, 16);
uint8_t msz = bits(machInst, 24, 23);
switch (msz) {
case 0:
@@ -3083,9 +3083,9 @@
return new Unknown64(machInst);
}
- IntRegIndex zt = (IntRegIndex)(uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex)(uint8_t) bits(machInst, 9, 5));
- IntRegIndex pg = (IntRegIndex)(uint8_t) bits(machInst, 12, 10);
+ RegIndex zt = (RegIndex)(uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex)(uint8_t) bits(machInst, 9, 5));
+ RegIndex pg = (RegIndex)(uint8_t) bits(machInst, 12, 10);
uint64_t imm = sext<4>(bits(machInst, 19, 16));
uint8_t msz = bits(machInst, 24, 23);
switch (msz) {
@@ -3109,10 +3109,10 @@
StaticInstPtr
decodeSveContigLoadSS(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
if (rm == 0x1f) {
return new Unknown64(machInst);
@@ -3125,10 +3125,10 @@
StaticInstPtr
decodeSveContigFFLoadSS(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
return decodeSveContigLoadSSInsts<SveContigFFLoadSS>(
bits(machInst, 24, 21), machInst, zt, pg, rn, rm, true);
@@ -3137,10 +3137,10 @@
StaticInstPtr
decodeSveContigLoadSI(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex) (uint8_t) bits(machInst, 9, 5));
uint64_t imm = sext<4>(bits(machInst, 19, 16));
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
return decodeSveContigLoadSIInsts<SveContigLoadSI>(
bits(machInst, 24, 21), machInst, zt, pg, rn, imm, false);
@@ -3149,10 +3149,10 @@
StaticInstPtr
decodeSveContigNFLoadSI(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex) (uint8_t) bits(machInst, 9, 5));
uint64_t imm = sext<4>(bits(machInst, 19, 16));
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
return decodeSveContigLoadSIInsts<SveContigNFLoadSI>(
bits(machInst, 24, 21), machInst, zt, pg, rn, imm, true);
@@ -3167,11 +3167,11 @@
StaticInstPtr
decodeSveLoadStructsSS(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
uint8_t num = bits(machInst, 22, 21);
@@ -3192,11 +3192,11 @@
StaticInstPtr
decodeSveLoadStructsSI(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
int64_t imm = sext<4>(bits(machInst, 19, 16));
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
uint8_t num = bits(machInst, 22, 21);
@@ -3257,12 +3257,12 @@
{
// SVE 64-bit gather load (scalar plus unpacked 32-bit unscaled
// offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 1) |
bits(machInst, 14);
@@ -3275,12 +3275,12 @@
case 0x1:
if (bits(machInst, 22)) {
// SVE 64-bit gather load (scalar plus 64-bit unscaled offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 1) |
bits(machInst, 14);
@@ -3299,12 +3299,12 @@
if (bits(machInst, 24, 23) != 0x0) {
// SVE 64-bit gather load (scalar plus unpacked 32-bit scaled
// offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 1) |
bits(machInst, 14);
@@ -3322,10 +3322,10 @@
case 0x3:
if (bits(machInst, 22) == 0) {
// SVE 64-bit gather load (vector plus immediate)
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t) bits(machInst, 9, 5);
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex zn = (RegIndex) (uint8_t) bits(machInst, 9, 5);
uint64_t imm = bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 1) |
bits(machInst, 14);
@@ -3336,13 +3336,13 @@
if (bits(machInst, 24, 23) != 0x0) {
// SVE 64-bit gather load (scalar plus 64-bit scaled
// offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t dtype = (bits(machInst, 24, 23) << 1) |
bits(machInst, 14);
@@ -3364,10 +3364,10 @@
StaticInstPtr
decodeSveContigStoreSS(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
if (rm == 0x1f) {
return new Unknown64(machInst);
@@ -3380,10 +3380,10 @@
StaticInstPtr
decodeSveContigStoreSI(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP((IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP((RegIndex) (uint8_t) bits(machInst, 9, 5));
int8_t imm = sext<4>(bits(machInst, 19, 16));
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
return decodeSveContigStoreSIInsts<SveContigStoreSI>(
bits(machInst, 24, 21), machInst, zt, pg, rn, imm);
@@ -3404,11 +3404,11 @@
StaticInstPtr
decodeSveStoreStructsSS(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex rm = (IntRegIndex) (uint8_t) bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex rm = (RegIndex) (uint8_t) bits(machInst, 20, 16);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
uint8_t num = bits(machInst, 22, 21);
@@ -3423,11 +3423,11 @@
StaticInstPtr
decodeSveStoreStructsSI(ExtMachInst machInst)
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
int64_t imm = sext<4>(bits(machInst, 19, 16));
- IntRegIndex pg = (IntRegIndex) (uint8_t) bits(machInst, 12, 10);
+ RegIndex pg = (RegIndex) (uint8_t) bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
uint8_t num = bits(machInst, 22, 21);
@@ -3446,9 +3446,9 @@
switch (bits(machInst, 15, 13)) {
case 0x0:
if (bits(machInst, 24, 22) == 0x6 && bits(machInst, 4) == 0x0) {
- IntRegIndex pt = (IntRegIndex) (uint8_t) bits(machInst, 3, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex pt = (RegIndex) (uint8_t) bits(machInst, 3, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
int16_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
bits(machInst, 12, 10));
return new SveStrPred(machInst, pt, rn, imm);
@@ -3456,9 +3456,9 @@
break;
case 0x2:
if (bits(machInst, 24, 22) == 0x6) {
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
int16_t imm = sext<9>((bits(machInst, 21, 16) << 3) |
bits(machInst, 12, 10));
return new SveStrVec(machInst, zt, rn, imm);
@@ -3475,12 +3475,12 @@
case 0x4:
case 0x6:
{
- IntRegIndex zt = (IntRegIndex) (uint8_t) bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t) bits(machInst, 4, 0);
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
uint8_t xs = bits(machInst, 22);
@@ -3525,13 +3525,13 @@
{
// SVE 64-bit scatter store (scalar plus 64-bit unscaled
// offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
@@ -3543,13 +3543,13 @@
if (bits(machInst, 24, 23) != 0x0) {
// SVE 64-bit scatter store (scalar plus 64-bit scaled
// offsets)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex rn = makeSP(
- (IntRegIndex) (uint8_t) bits(machInst, 9, 5));
- IntRegIndex zm = (IntRegIndex) (uint8_t)
+ RegIndex rn = makeSP(
+ (RegIndex) (uint8_t) bits(machInst, 9, 5));
+ RegIndex zm = (RegIndex) (uint8_t)
bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
@@ -3561,12 +3561,12 @@
case 0x2:
{
// SVE 64-bit scatter store (vector plus immediate)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t)
+ RegIndex zn = (RegIndex) (uint8_t)
bits(machInst, 9, 5);
uint64_t imm = bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
@@ -3576,12 +3576,12 @@
case 0x3:
if (bits(machInst, 24, 23) != 0x3) {
// SVE 32-bit scatter store (vector plus immediate)
- IntRegIndex zt = (IntRegIndex) (uint8_t)
+ RegIndex zt = (RegIndex) (uint8_t)
bits(machInst, 4, 0);
- IntRegIndex zn = (IntRegIndex) (uint8_t)
+ RegIndex zn = (RegIndex) (uint8_t)
bits(machInst, 9, 5);
uint64_t imm = bits(machInst, 20, 16);
- IntRegIndex pg = (IntRegIndex) (uint8_t)
+ RegIndex pg = (RegIndex) (uint8_t)
bits(machInst, 12, 10);
uint8_t msz = bits(machInst, 24, 23);
diff --git a/src/arch/arm/isa/formats/uncond.isa b/src/arch/arm/isa/formats/uncond.isa
index dfa9214..813ca90 100644
--- a/src/arch/arm/isa/formats/uncond.isa
+++ b/src/arch/arm/isa/formats/uncond.isa
@@ -36,7 +36,7 @@
def format ArmUnconditional() {{
decode_block = '''
{
- const IntRegIndex rn = (IntRegIndex)(uint32_t)bits(machInst, 19, 16);
+ const RegIndex rn = (RegIndex)(uint32_t)bits(machInst, 19, 16);
const uint32_t op1 = bits(machInst, 27, 20);
if (bits(op1, 7) == 0) {
const uint32_t op2 = bits(machInst, 7, 4);
@@ -63,10 +63,10 @@
const bool add = bits(machInst, 23);
const uint32_t imm12 = bits(machInst, 11, 0);
if (add) {
- return new %(pli_iadd)s(machInst, INTREG_ZERO,
+ return new %(pli_iadd)s(machInst, int_reg::Zero,
rn, add, imm12);
} else {
- return new %(pli_isub)s(machInst, INTREG_ZERO,
+ return new %(pli_isub)s(machInst, int_reg::Zero,
rn, add, imm12);
}
}
@@ -77,18 +77,18 @@
const uint32_t imm12 = bits(machInst, 11, 0);
if (pldw) {
if (add) {
- return new %(pldw_iadd)s(machInst, INTREG_ZERO,
+ return new %(pldw_iadd)s(machInst, int_reg::Zero,
rn, add, imm12);
} else {
- return new %(pldw_isub)s(machInst, INTREG_ZERO,
+ return new %(pldw_isub)s(machInst, int_reg::Zero,
rn, add, imm12);
}
} else {
if (add) {
- return new %(pld_iadd)s(machInst, INTREG_ZERO,
+ return new %(pld_iadd)s(machInst, int_reg::Zero,
rn, add, imm12);
} else {
- return new %(pld_isub)s(machInst, INTREG_ZERO,
+ return new %(pld_isub)s(machInst, int_reg::Zero,
rn, add, imm12);
}
}
@@ -114,14 +114,14 @@
const uint32_t imm5 = bits(machInst, 11, 7);
const uint32_t type = bits(machInst, 6, 5);
const bool add = bits(machInst, 23);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
if (add) {
- return new %(pli_radd)s(machInst, INTREG_ZERO, rn,
- add, imm5, type, rm);
+ return new %(pli_radd)s(machInst, int_reg::Zero,
+ rn, add, imm5, type, rm);
} else {
- return new %(pli_rsub)s(machInst, INTREG_ZERO, rn,
- add, imm5, type, rm);
+ return new %(pli_rsub)s(machInst, int_reg::Zero,
+ rn, add, imm5, type, rm);
}
}
case 0x71:
@@ -131,25 +131,29 @@
const uint32_t type = bits(machInst, 6, 5);
const bool add = bits(machInst, 23);
const bool pldw = bits(machInst, 22);
- const IntRegIndex rm =
- (IntRegIndex)(uint32_t)bits(machInst, 3, 0);
+ const RegIndex rm =
+ (RegIndex)(uint32_t)bits(machInst, 3, 0);
if (pldw) {
if (add) {
- return new %(pldw_radd)s(machInst, INTREG_ZERO,
+ return new %(pldw_radd)s(machInst,
+ int_reg::Zero,
rn, add, imm5,
type, rm);
} else {
- return new %(pldw_rsub)s(machInst, INTREG_ZERO,
+ return new %(pldw_rsub)s(machInst,
+ int_reg::Zero,
rn, add, imm5,
type, rm);
}
} else {
if (add) {
- return new %(pld_radd)s(machInst, INTREG_ZERO,
+ return new %(pld_radd)s(machInst,
+ int_reg::Zero,
rn, add, imm5,
type, rm);
} else {
- return new %(pld_rsub)s(machInst, INTREG_ZERO,
+ return new %(pld_rsub)s(machInst,
+ int_reg::Zero,
rn, add, imm5,
type, rm);
}
@@ -244,7 +248,7 @@
return decodeExtensionRegLoadStore(machInst);
}
if (bits(op1, 0) == 1) {
- if (rn == INTREG_PC) {
+ if (rn == int_reg::Pc) {
if (bits(op1, 4, 3) != 0x0) {
return new WarnUnimplemented(
"ldc, ldc2 (literal)", machInst);
diff --git a/src/arch/arm/isa/insts/branch.isa b/src/arch/arm/isa/insts/branch.isa
index fd48bad..c14e1f8 100644
--- a/src/arch/arm/isa/insts/branch.isa
+++ b/src/arch/arm/isa/insts/branch.isa
@@ -122,7 +122,7 @@
instFlags += ["IsCall"]
else:
linkStr = ""
- isRasPop = "op1 == INTREG_LR"
+ isRasPop = "op1 == int_reg::Lr"
if imm and link: #blx with imm
branchStr = '''
@@ -161,7 +161,7 @@
bxjIop = ArmInstObjParams("bxj", "BxjReg", "BranchRegCond",
{ "code": bxjcode,
"predicate_test": predicateTest,
- "is_ras_pop": "op1 == INTREG_LR" },
+ "is_ras_pop": "op1 == int_reg::Lr" },
["IsIndirectControl"])
header_output += BranchRegCondDeclare.subst(bxjIop)
decoder_output += BranchRegCondConstructor.subst(bxjIop)
diff --git a/src/arch/arm/isa/insts/data.isa b/src/arch/arm/isa/insts/data.isa
index d7a957d..9a14d97 100644
--- a/src/arch/arm/isa/insts/data.isa
+++ b/src/arch/arm/isa/insts/data.isa
@@ -285,14 +285,14 @@
buildDataInst("and", "Dest = resTemp = Op1 & secondOp;")
buildDataInst("eor", "Dest = resTemp = Op1 ^ secondOp;")
buildDataInst("sub", "Dest = resTemp = Op1 - secondOp;", "sub",
- isBranch = "dest == INTREG_PC")
+ isBranch = "dest == int_reg::Pc")
buildDataInst("rsb", "Dest = resTemp = secondOp - Op1;", "rsb")
buildDataInst("add", "Dest = resTemp = Op1 + secondOp;", "add",
- isBranch = "dest == INTREG_PC")
+ isBranch = "dest == int_reg::Pc")
buildImmDataInst("adr", '''
Dest = resTemp = (PC & ~0x3) +
(op1 ? secondOp : -secondOp);
- ''', isBranch = "dest == INTREG_PC")
+ ''', isBranch = "dest == int_reg::Pc")
buildDataInst("adc", "Dest = resTemp = Op1 + secondOp + %s;" % oldC, "add")
buildDataInst("sbc", "Dest = resTemp = Op1 - secondOp - !%s;" % oldC, "sub")
buildDataInst("rsc", "Dest = resTemp = secondOp - Op1 - !%s;" % oldC, "rsb")
@@ -303,7 +303,8 @@
buildDataInst("orr", "Dest = resTemp = Op1 | secondOp;")
buildDataInst("orn", "Dest = resTemp = Op1 | ~secondOp;", aiw = False)
buildDataInst("mov", "Dest = resTemp = secondOp;", regRegAiw = False,
- isRasPop = "op2 == INTREG_LR", isBranch = "dest == INTREG_PC")
+ isRasPop = "op2 == int_reg::Lr",
+ isBranch = "dest == int_reg::Pc")
buildDataInst("bic", "Dest = resTemp = Op1 & ~secondOp;")
buildDataInst("mvn", "Dest = resTemp = ~secondOp;")
buildDataInst("movt",
diff --git a/src/arch/arm/isa/insts/fp.isa b/src/arch/arm/isa/insts/fp.isa
index bb65d5b..00f2b80 100644
--- a/src/arch/arm/isa/insts/fp.isa
+++ b/src/arch/arm/isa/insts/fp.isa
@@ -41,8 +41,8 @@
class VfpMacroRegRegOp : public VfpMacroOp
{
public:
- VfpMacroRegRegOp(ExtMachInst _machInst, IntRegIndex _dest,
- IntRegIndex _op1, bool _wide) :
+ VfpMacroRegRegOp(ExtMachInst _machInst, RegIndex _dest,
+ RegIndex _op1, bool _wide) :
VfpMacroOp("VfpMacroRegRegOp", _machInst, No_OpClass, _wide)
{
numMicroops = machInst.fpscrLen + 1;
@@ -63,7 +63,7 @@
template <class VfpOp>
StaticInstPtr
decodeVfpRegRegOp(ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, bool wide)
+ RegIndex dest, RegIndex op1, bool wide)
{
if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) {
return new VfpOp(machInst, dest, op1);
@@ -76,7 +76,7 @@
class VfpMacroRegImmOp : public VfpMacroOp
{
public:
- VfpMacroRegImmOp(ExtMachInst _machInst, IntRegIndex _dest, uint64_t _imm,
+ VfpMacroRegImmOp(ExtMachInst _machInst, RegIndex _dest, uint64_t _imm,
bool _wide) :
VfpMacroOp("VfpMacroRegImmOp", _machInst, No_OpClass, _wide)
{
@@ -97,7 +97,7 @@
template <class VfpOp>
StaticInstPtr
decodeVfpRegImmOp(ExtMachInst machInst,
- IntRegIndex dest, uint64_t imm, bool wide)
+ RegIndex dest, uint64_t imm, bool wide)
{
if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) {
return new VfpOp(machInst, dest, imm);
@@ -110,8 +110,8 @@
class VfpMacroRegRegImmOp : public VfpMacroOp
{
public:
- VfpMacroRegRegImmOp(ExtMachInst _machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm, bool _wide) :
+ VfpMacroRegRegImmOp(ExtMachInst _machInst, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm, bool _wide) :
VfpMacroOp("VfpMacroRegRegImmOp", _machInst, No_OpClass, _wide)
{
numMicroops = machInst.fpscrLen + 1;
@@ -130,8 +130,8 @@
template <class VfpOp>
StaticInstPtr
-decodeVfpRegRegImmOp(ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm, bool wide)
+decodeVfpRegRegImmOp(ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm, bool wide)
{
if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) {
return new VfpOp(machInst, dest, op1, imm);
@@ -144,8 +144,8 @@
class VfpMacroRegRegRegOp : public VfpMacroOp
{
public:
- VfpMacroRegRegRegOp(ExtMachInst _machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, bool _wide) :
+ VfpMacroRegRegRegOp(ExtMachInst _machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, bool _wide) :
VfpMacroOp("VfpMacroRegRegRegOp", _machInst, No_OpClass, _wide)
{
numMicroops = machInst.fpscrLen + 1;
@@ -164,8 +164,8 @@
template <class VfpOp>
StaticInstPtr
-decodeVfpRegRegRegOp(ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2, bool wide)
+decodeVfpRegRegRegOp(ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2, bool wide)
{
if (machInst.fpscrLen == 0 || VfpMacroOp::inScalarBank(dest)) {
return new VfpOp(machInst, dest, op1, op2);
diff --git a/src/arch/arm/isa/insts/ldr.isa b/src/arch/arm/isa/insts/ldr.isa
index 1f011bc..2e82ab2 100644
--- a/src/arch/arm/isa/insts/ldr.isa
+++ b/src/arch/arm/isa/insts/ldr.isa
@@ -118,7 +118,8 @@
self.codeBlobs["memacc_code"] = accCode
wbDecl = None
- pcDecl = "MicroUopSetPCCPSR(machInst, INTREG_UREG0, INTREG_UREG1, INTREG_UREG2);"
+ pcDecl = "MicroUopSetPCCPSR(machInst, int_reg::Ureg0, " \
+ "int_reg::Ureg1, int_reg::Ureg2);"
if self.writeback:
wbDecl = "MicroAddiUop(machInst, base, base, %d);" % wbDiff
diff --git a/src/arch/arm/isa/insts/macromem.isa b/src/arch/arm/isa/insts/macromem.isa
index 94acf41..edd7228 100644
--- a/src/arch/arm/isa/insts/macromem.isa
+++ b/src/arch/arm/isa/insts/macromem.isa
@@ -610,7 +610,7 @@
microAddXiSpAlignUopIop = ArmInstObjParams('addxi_uop',
'MicroAddXiSpAlignUop', 'MicroIntImmXOp', '''
- if (isSP((IntRegIndex) urb) && bits(XURb, 3, 0) &&
+ if (isSP((RegIndex) urb) && bits(XURb, 3, 0) &&
SPAlignmentCheckEnabled(xc->tcBase())) {
return std::make_shared<SPAlignmentFault>();
}
diff --git a/src/arch/arm/isa/insts/mem.isa b/src/arch/arm/isa/insts/mem.isa
index 760a354..a7add8a 100644
--- a/src/arch/arm/isa/insts/mem.isa
+++ b/src/arch/arm/isa/insts/mem.isa
@@ -66,7 +66,7 @@
codeBlobs["fa_code"] = faCode
elif wbDecl == None:
codeBlobs["fa_code"] = '''
- if (dest != INTREG_PC) {
+ if (dest != int_reg::Pc) {
fault->annotate(ArmISA::ArmFault::SAS, %s);
fault->annotate(ArmISA::ArmFault::SSE, %s);
fault->annotate(ArmISA::ArmFault::SRT, dest);
diff --git a/src/arch/arm/isa/insts/misc.isa b/src/arch/arm/isa/insts/misc.isa
index e11a65d..6083407 100644
--- a/src/arch/arm/isa/insts/misc.isa
+++ b/src/arch/arm/isa/insts/misc.isa
@@ -290,7 +290,7 @@
// you look at the generated C code you'll find that they are.
// However this is safe as DecodedBankedIntReg (which is used
// in operands.isa to get the index of DecodedBankedIntReg)
- // will return INTREG_ZERO if its not a valid integer
+ // will return int_reg::Zero if its not a valid integer
// register, so redirecting the write to somewhere we don't
// care about.
DecodedBankedIntReg = Op1;
diff --git a/src/arch/arm/isa/insts/neon.isa b/src/arch/arm/isa/insts/neon.isa
index 756abdc..df2bd3a 100644
--- a/src/arch/arm/isa/insts/neon.isa
+++ b/src/arch/arm/isa/insts/neon.isa
@@ -39,8 +39,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUThreeUReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 0:
@@ -59,8 +59,8 @@
template <class BaseS, class BaseD>
StaticInstPtr
decodeNeonSizeSingleDouble(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 2:
@@ -75,8 +75,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSThreeUReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 0:
@@ -95,8 +95,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUSThreeUReg(bool notSigned, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (notSigned) {
return decodeNeonUThreeUReg<Base>(size, machInst, dest, op1, op2);
@@ -108,8 +108,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUThreeUSReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 0:
@@ -126,8 +126,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSThreeUSReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 0:
@@ -144,8 +144,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSThreeHAndWReg(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex op2)
+ RegIndex dest, RegIndex op1,
+ RegIndex op2)
{
switch (size) {
case 1:
@@ -160,8 +160,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSThreeImmHAndWReg(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex op2, uint64_t imm)
+ RegIndex dest, RegIndex op1,
+ RegIndex op2, uint64_t imm)
{
switch (size) {
case 1:
@@ -176,8 +176,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUSThreeUSReg(bool notSigned, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (notSigned) {
return decodeNeonUThreeUSReg<Base>(
@@ -192,8 +192,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUThreeSReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (q) {
return decodeNeonUThreeUSReg<BaseQ>(
@@ -208,8 +208,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSThreeSReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (q) {
return decodeNeonSThreeUSReg<BaseQ>(
@@ -224,8 +224,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSThreeXReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (q) {
return decodeNeonSThreeUReg<BaseQ>(
@@ -240,8 +240,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUThreeXReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (q) {
return decodeNeonUThreeUReg<BaseQ>(
@@ -256,8 +256,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUSThreeSReg(bool q, bool notSigned, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (notSigned) {
return decodeNeonUThreeSReg<BaseD, BaseQ>(
@@ -272,8 +272,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUThreeReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (q) {
return decodeNeonUThreeUReg<BaseQ>(
@@ -288,8 +288,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSThreeReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (q) {
return decodeNeonSThreeUReg<BaseQ>(
@@ -304,8 +304,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUSThreeReg(bool q, bool notSigned, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
if (notSigned) {
return decodeNeonUThreeReg<BaseD, BaseQ>(
@@ -320,7 +320,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUThreeFpReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2)
+ RegIndex dest, RegIndex op1, RegIndex op2)
{
if (q) {
if (size)
@@ -338,7 +338,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUThreeScFpReg(bool size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2)
+ RegIndex dest, RegIndex op1, RegIndex op2)
{
if (size)
return new Base<uint64_t>(machInst, dest, op1, op2);
@@ -349,8 +349,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUThreeImmScFpReg(bool size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex op2, uint64_t imm)
+ RegIndex dest, RegIndex op1,
+ RegIndex op2, uint64_t imm)
{
if (size)
return new Base<uint64_t>(machInst, dest, op1, op2, imm);
@@ -362,8 +362,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUThreeImmHAndWReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex op2, uint64_t imm)
+ RegIndex dest, RegIndex op1,
+ RegIndex op2, uint64_t imm)
{
if (q) {
switch (size) {
@@ -390,8 +390,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSThreeImmHAndWReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex op2, uint64_t imm)
+ RegIndex dest, RegIndex op1,
+ RegIndex op2, uint64_t imm)
{
if (q) {
switch (size) {
@@ -418,8 +418,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUThreeImmFpReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex op2, uint64_t imm)
+ RegIndex dest, RegIndex op1,
+ RegIndex op2, uint64_t imm)
{
if (q) {
if (size)
@@ -438,8 +438,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoShiftReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
if (q) {
switch (size) {
@@ -474,8 +474,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSTwoShiftReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
if (q) {
switch (size) {
@@ -511,8 +511,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUSTwoShiftReg(bool q, bool notSigned, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
if (notSigned) {
return decodeNeonUTwoShiftReg<BaseD, BaseQ>(
@@ -526,8 +526,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUTwoShiftUSReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
switch (size) {
case 0:
@@ -544,8 +544,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUTwoShiftUReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
switch (size) {
case 0:
@@ -564,8 +564,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSTwoShiftUReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
switch (size) {
case 0:
@@ -585,8 +585,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoShiftSReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
if (q) {
return decodeNeonUTwoShiftUSReg<BaseQ>(
@@ -600,8 +600,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSTwoShiftUSReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
switch (size) {
case 0:
@@ -619,8 +619,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSTwoShiftSReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
if (q) {
return decodeNeonSTwoShiftUSReg<BaseQ>(
@@ -635,8 +635,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUSTwoShiftSReg(bool q, bool notSigned, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, uint64_t imm)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, uint64_t imm)
{
if (notSigned) {
return decodeNeonUTwoShiftSReg<BaseD, BaseQ>(
@@ -651,7 +651,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoShiftXReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, uint64_t imm)
+ RegIndex dest, RegIndex op1, uint64_t imm)
{
if (q) {
return decodeNeonUTwoShiftUReg<BaseQ>(
@@ -666,7 +666,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSTwoShiftXReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, uint64_t imm)
+ RegIndex dest, RegIndex op1, uint64_t imm)
{
if (q) {
return decodeNeonSTwoShiftUReg<BaseQ>(
@@ -680,7 +680,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUTwoShiftUFpReg(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, uint64_t imm)
+ RegIndex dest, RegIndex op1, uint64_t imm)
{
if (size)
return new Base<uint64_t>(machInst, dest, op1, imm);
@@ -692,7 +692,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoShiftFpReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, uint64_t imm)
+ RegIndex dest, RegIndex op1, uint64_t imm)
{
if (q) {
if (size)
@@ -710,8 +710,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUTwoMiscUSReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
switch (size) {
case 0:
@@ -728,8 +728,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSTwoMiscUSReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
switch (size) {
case 0:
@@ -747,8 +747,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoMiscSReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
if (q) {
return decodeNeonUTwoMiscUSReg<BaseQ>(size, machInst, dest, op1);
@@ -761,8 +761,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSTwoMiscSReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
if (q) {
return decodeNeonSTwoMiscUSReg<BaseQ>(size, machInst, dest, op1);
@@ -774,8 +774,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUTwoMiscUReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
switch (size) {
case 0:
@@ -794,8 +794,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonSTwoMiscUReg(unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
switch (size) {
case 0:
@@ -815,8 +815,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSTwoMiscReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
if (q) {
return decodeNeonSTwoMiscUReg<BaseQ>(size, machInst, dest, op1);
@@ -829,8 +829,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoMiscReg(bool q, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
if (q) {
return decodeNeonUTwoMiscUReg<BaseQ>(size, machInst, dest, op1);
@@ -843,8 +843,8 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUSTwoMiscSReg(bool q, bool notSigned, unsigned size,
- ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1)
+ ExtMachInst machInst, RegIndex dest,
+ RegIndex op1)
{
if (notSigned) {
return decodeNeonUTwoShiftSReg<BaseD, BaseQ>(
@@ -859,7 +859,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoMiscXReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
return decodeNeonUTwoMiscUReg<BaseQ>(size, machInst, dest, op1);
@@ -872,7 +872,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSTwoMiscXReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
return decodeNeonSTwoMiscUReg<BaseQ>(size, machInst, dest, op1);
@@ -885,7 +885,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoMiscFpReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
if (size)
@@ -904,7 +904,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUTwoMiscPwiseScFpReg(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (size)
return new BaseQ<uint64_t>(machInst, dest, op1);
@@ -915,7 +915,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeNeonUTwoMiscScFpReg(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (size)
return new Base<uint64_t>(machInst, dest, op1);
@@ -927,7 +927,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonUAcrossLanesReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
switch (size) {
@@ -957,7 +957,7 @@
template <typename T> class BaseBQ>
StaticInstPtr
decodeNeonUAcrossLanesReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
switch (size) {
@@ -986,7 +986,7 @@
template <typename T> class BaseQ>
StaticInstPtr
decodeNeonSAcrossLanesReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
switch (size) {
@@ -1016,7 +1016,7 @@
template <typename T> class BaseBQ>
StaticInstPtr
decodeNeonUAcrossLanesLongReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
switch (size) {
@@ -1046,7 +1046,7 @@
template <typename T> class BaseBQ>
StaticInstPtr
decodeNeonSAcrossLanesLongReg(bool q, unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
if (q) {
switch (size) {
diff --git a/src/arch/arm/isa/insts/str.isa b/src/arch/arm/isa/insts/str.isa
index 8700293..1583ef0 100644
--- a/src/arch/arm/isa/insts/str.isa
+++ b/src/arch/arm/isa/insts/str.isa
@@ -130,8 +130,10 @@
wbDecl = None
if self.writeback:
wbDecl = '''MicroAddiUop(machInst,
- intRegInMode((OperatingMode)regMode, INTREG_SP),
- intRegInMode((OperatingMode)regMode, INTREG_SP),
+ int_reg::regInMode((OperatingMode)regMode,
+ int_reg::Sp),
+ int_reg::regInMode((OperatingMode)regMode,
+ int_reg::Sp),
%d);''' % wbDiff
(newHeader,
diff --git a/src/arch/arm/isa/insts/sve.isa b/src/arch/arm/isa/insts/sve.isa
index 7338eb2..7cb7331 100644
--- a/src/arch/arm/isa/insts/sve.isa
+++ b/src/arch/arm/isa/insts/sve.isa
@@ -43,7 +43,7 @@
template <typename T> class BaseU>
StaticInstPtr
decodeSveUnaryPred(unsigned size, unsigned u, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex gp)
{
switch (size) {
case 0:
@@ -81,7 +81,7 @@
template <typename T1, typename T2> class BaseU>
StaticInstPtr
decodeSveWideningReduc(unsigned size, unsigned u, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex gp)
{
switch (size) {
case 0:
@@ -115,7 +115,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveUnaryPredS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex gp)
{
switch (size) {
case 0:
@@ -136,7 +136,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveUnaryPredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex gp)
{
switch (size) {
case 0:
@@ -159,7 +159,7 @@
template <typename T> class BaseU>
StaticInstPtr
decodeSveUnaryPredSmall(unsigned size, unsigned u, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex gp)
{
switch (size) {
case 0:
@@ -190,7 +190,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveUnaryPredF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex gp)
{
switch (size) {
case 1:
@@ -209,7 +209,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveUnaryUnpredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 0:
@@ -230,7 +230,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveUnaryUnpredF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 1:
@@ -250,7 +250,7 @@
template <typename T> class BaseU>
StaticInstPtr
decodeSveBinDestrPred(unsigned size, unsigned u, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op2, IntRegIndex gp)
+ RegIndex dest, RegIndex op2, RegIndex gp)
{
switch (size) {
case 0:
@@ -287,7 +287,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveBinImmUnpredS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, unsigned immediate)
+ RegIndex dest, RegIndex op1, unsigned immediate)
{
switch (size) {
case 0:
@@ -309,7 +309,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveBinImmUnpredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, unsigned immediate)
+ RegIndex dest, RegIndex op1, unsigned immediate)
{
switch (size) {
case 0:
@@ -329,8 +329,8 @@
// SVE instructions, handling unsigned variants only.
template <template <typename T> class Base>
StaticInstPtr
- decodeSveBinImmPredU(unsigned size, ExtMachInst machInst, IntRegIndex dest,
- unsigned immediate, IntRegIndex gp)
+ decodeSveBinImmPredU(unsigned size, ExtMachInst machInst, RegIndex dest,
+ unsigned immediate, RegIndex gp)
{
switch (size) {
case 0:
@@ -350,8 +350,8 @@
// SVE instructions, handling signed variants only.
template <template <typename T> class Base>
StaticInstPtr
- decodeSveBinImmPredS(unsigned size, ExtMachInst machInst, IntRegIndex dest,
- unsigned immediate, IntRegIndex gp)
+ decodeSveBinImmPredS(unsigned size, ExtMachInst machInst, RegIndex dest,
+ unsigned immediate, RegIndex gp)
{
switch (size) {
case 0:
@@ -371,8 +371,8 @@
// SVE instructions, handling floating-point variants only.
template <template <typename T> class Base>
StaticInstPtr
- decodeSveBinImmPredF(unsigned size, ExtMachInst machInst, IntRegIndex dest,
- uint64_t immediate, IntRegIndex gp)
+ decodeSveBinImmPredF(unsigned size, ExtMachInst machInst, RegIndex dest,
+ uint64_t immediate, RegIndex gp)
{
switch (size) {
case 1:
@@ -391,7 +391,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveWideImmUnpredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint64_t immediate)
+ RegIndex dest, uint64_t immediate)
{
switch (size) {
case 0:
@@ -412,7 +412,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveWideImmUnpredS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint64_t immediate)
+ RegIndex dest, uint64_t immediate)
{
switch (size) {
case 0:
@@ -433,7 +433,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveWideImmUnpredF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint64_t immediate)
+ RegIndex dest, uint64_t immediate)
{
switch (size) {
case 1:
@@ -452,7 +452,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveWideImmPredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint64_t immediate, IntRegIndex gp,
+ RegIndex dest, uint64_t immediate, RegIndex gp,
bool isMerging = true)
{
switch (size) {
@@ -478,7 +478,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveWideImmPredF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint64_t immediate, IntRegIndex gp)
+ RegIndex dest, uint64_t immediate, RegIndex gp)
{
switch (size) {
case 1:
@@ -497,7 +497,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveBinDestrPredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op2, IntRegIndex gp)
+ RegIndex dest, RegIndex op2, RegIndex gp)
{
switch (size) {
case 0:
@@ -518,7 +518,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveBinDestrPredS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op2, IntRegIndex gp)
+ RegIndex dest, RegIndex op2, RegIndex gp)
{
switch (size) {
case 0:
@@ -539,7 +539,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveBinDestrPredF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op2, IntRegIndex gp)
+ RegIndex dest, RegIndex op2, RegIndex gp)
{
switch (size) {
case 1:
@@ -558,8 +558,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveBinConstrPredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp, SvePredType predType)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp, SvePredType predType)
{
switch (size) {
case 0:
@@ -579,7 +579,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveBinUnpred(unsigned size, unsigned u, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2)
+ RegIndex dest, RegIndex op1, RegIndex op2)
{
switch (size) {
case 0:
@@ -615,8 +615,8 @@
// Unsigned instructions only.
template <template <typename T> class Base>
StaticInstPtr
- decodeSveBinUnpredU(unsigned size, ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ decodeSveBinUnpredU(unsigned size, ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 0:
@@ -636,8 +636,8 @@
// Signed instructions only.
template <template <typename T> class Base>
StaticInstPtr
- decodeSveBinUnpredS(unsigned size, ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ decodeSveBinUnpredS(unsigned size, ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 0:
@@ -657,8 +657,8 @@
// floating-point variants only.
template <template <typename T> class Base>
StaticInstPtr
- decodeSveBinUnpredF(unsigned size, ExtMachInst machInst, IntRegIndex dest,
- IntRegIndex op1, IntRegIndex op2)
+ decodeSveBinUnpredF(unsigned size, ExtMachInst machInst, RegIndex dest,
+ RegIndex op1, RegIndex op2)
{
switch (size) {
case 1:
@@ -677,8 +677,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveCmpF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp)
{
switch (size) {
case 1:
@@ -698,8 +698,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveCmpImmF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, uint64_t imm,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, uint64_t imm,
+ RegIndex gp)
{
switch (size) {
case 1:
@@ -717,8 +717,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerPred(unsigned size, unsigned u, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp)
{
switch (size) {
case 0:
@@ -755,8 +755,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerPredWS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp)
{
switch (size) {
case 0:
@@ -775,8 +775,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerPredWU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp)
{
switch (size) {
case 0:
@@ -795,8 +795,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerPredS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp)
{
switch (size) {
case 0:
@@ -817,8 +817,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerPredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp)
{
switch (size) {
case 0:
@@ -839,8 +839,8 @@
template <template <typename TS, typename TD> class Base>
StaticInstPtr
decodeSveUnaryExtendFromBPredS(unsigned dsize, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1,
+ RegIndex gp)
{
switch (dsize) {
case 1:
@@ -858,8 +858,8 @@
template <template <typename TS, typename TD> class Base>
StaticInstPtr
decodeSveUnaryExtendFromBPredU(unsigned dsize, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1,
+ RegIndex gp)
{
switch (dsize) {
case 1:
@@ -877,8 +877,8 @@
template <template <typename TS, typename TD> class Base>
StaticInstPtr
decodeSveUnaryExtendFromHPredS(unsigned dsize, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1,
+ RegIndex gp)
{
switch (dsize) {
case 2:
@@ -894,8 +894,8 @@
template <template <typename TS, typename TD> class Base>
StaticInstPtr
decodeSveUnaryExtendFromHPredU(unsigned dsize, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1,
+ RegIndex gp)
{
switch (dsize) {
case 2:
@@ -911,8 +911,8 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerPredF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, IntRegIndex op2,
- IntRegIndex gp)
+ RegIndex dest, RegIndex op1, RegIndex op2,
+ RegIndex gp)
{
switch (size) {
case 1:
@@ -931,7 +931,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerImmUnpredF(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op2, uint8_t imm)
+ RegIndex dest, RegIndex op2, uint8_t imm)
{
switch (size) {
case 1:
@@ -949,7 +949,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSvePtrue(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint8_t imm)
+ RegIndex dest, uint8_t imm)
{
switch (size) {
case 0:
@@ -969,7 +969,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSvePredCountS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 0:
@@ -989,7 +989,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSvePredCountU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 0:
@@ -1009,7 +1009,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSvePredCountVS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 1:
@@ -1027,7 +1027,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSvePredCountVU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 1:
@@ -1046,7 +1046,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerImmPredU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, int64_t imm, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, int64_t imm, RegIndex gp)
{
switch (size) {
case 0:
@@ -1067,7 +1067,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveTerImmPredS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1, int64_t imm, IntRegIndex gp)
+ RegIndex dest, RegIndex op1, int64_t imm, RegIndex gp)
{
switch (size) {
case 0:
@@ -1088,7 +1088,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveElemIntCountS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint8_t pattern, uint8_t imm4)
+ RegIndex dest, uint8_t pattern, uint8_t imm4)
{
switch (size) {
case 0:
@@ -1109,7 +1109,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveElemIntCountU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint8_t pattern, uint8_t imm4)
+ RegIndex dest, uint8_t pattern, uint8_t imm4)
{
switch (size) {
case 0:
@@ -1130,7 +1130,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveElemIntCountLS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint8_t pattern, uint8_t imm4)
+ RegIndex dest, uint8_t pattern, uint8_t imm4)
{
switch (size) {
case 1:
@@ -1149,7 +1149,7 @@
template <template <typename T> class Base>
StaticInstPtr
decodeSveElemIntCountLU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, uint8_t pattern, uint8_t imm4)
+ RegIndex dest, uint8_t pattern, uint8_t imm4)
{
switch (size) {
case 1:
@@ -1167,7 +1167,7 @@
template <template <typename T1, typename T2> class Base>
StaticInstPtr
decodeSveUnpackS(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 1:
@@ -1185,7 +1185,7 @@
template <template <typename T1, typename T2> class Base>
StaticInstPtr
decodeSveUnpackU(unsigned size, ExtMachInst machInst,
- IntRegIndex dest, IntRegIndex op1)
+ RegIndex dest, RegIndex op1)
{
switch (size) {
case 1:
diff --git a/src/arch/arm/isa/insts/sve_mem.isa b/src/arch/arm/isa/insts/sve_mem.isa
index 213f57d..8a73d13 100644
--- a/src/arch/arm/isa/insts/sve_mem.isa
+++ b/src/arch/arm/isa/insts/sve_mem.isa
@@ -41,8 +41,8 @@
template <template <typename T1, typename T2> class Base>
StaticInstPtr
decodeSveContigLoadSSInsts(uint8_t dtype, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex rn,
- IntRegIndex rm, bool firstFaulting)
+ RegIndex zt, RegIndex pg, RegIndex rn,
+ RegIndex rm, bool firstFaulting)
{
const char* mn = firstFaulting ? "ldff1" : "ld1";
switch (dtype) {
@@ -86,7 +86,7 @@
template <template <typename T1, typename T2> class Base>
StaticInstPtr
decodeSveContigLoadSIInsts(uint8_t dtype, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex rn,
+ RegIndex zt, RegIndex pg, RegIndex rn,
uint64_t imm, bool nonFaulting,
bool replicate = false)
{
@@ -133,8 +133,8 @@
template <template <typename T1, typename T2> class Base>
StaticInstPtr
decodeSveContigStoreSSInsts(uint8_t dtype, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex rn,
- IntRegIndex rm)
+ RegIndex zt, RegIndex pg, RegIndex rn,
+ RegIndex rm)
{
const char* mn = "st1";
switch (dtype) {
@@ -166,7 +166,7 @@
template <template <typename T1, typename T2> class Base>
StaticInstPtr
decodeSveContigStoreSIInsts(uint8_t dtype, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex rn,
+ RegIndex zt, RegIndex pg, RegIndex rn,
int8_t imm)
{
const char* mn = "st1";
@@ -205,7 +205,7 @@
template <class etype>
StaticInstPtr
decodeSveStructLoadSIInstsByNReg(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
+ RegIndex zt, RegIndex pg, RegIndex xn,
int64_t imm, int numregs)
{
static const char* nm[5][4] = {
@@ -240,7 +240,7 @@
StaticInstPtr
decodeSveStructLoadSIInsts(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
+ RegIndex zt, RegIndex pg, RegIndex xn,
int64_t imm, int numregs)
{
switch (esize) {
@@ -263,7 +263,7 @@
template <class etype>
StaticInstPtr
decodeSveStructStoreSIInstsByNReg(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
+ RegIndex zt, RegIndex pg, RegIndex xn,
int64_t imm, int numregs)
{
static const char* nm[5][4] = {
@@ -298,7 +298,7 @@
StaticInstPtr
decodeSveStructStoreSIInsts(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
+ RegIndex zt, RegIndex pg, RegIndex xn,
int64_t imm, int numregs)
{
switch (esize) {
@@ -321,8 +321,8 @@
template <class etype>
StaticInstPtr
decodeSveStructLoadSSInstsByNReg(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
- IntRegIndex xm, int numregs)
+ RegIndex zt, RegIndex pg, RegIndex xn,
+ RegIndex xm, int numregs)
{
static const char* nm[5][4] = {
{ nullptr, nullptr, nullptr, nullptr},
@@ -356,8 +356,8 @@
StaticInstPtr
decodeSveStructLoadSSInsts(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
- IntRegIndex xm, int numregs)
+ RegIndex zt, RegIndex pg, RegIndex xn,
+ RegIndex xm, int numregs)
{
switch (esize) {
case 0:
@@ -379,8 +379,8 @@
template <class etype>
StaticInstPtr
decodeSveStructStoreSSInstsByNReg(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
- IntRegIndex xm, int numregs)
+ RegIndex zt, RegIndex pg, RegIndex xn,
+ RegIndex xm, int numregs)
{
static const char* nm[5][4] = {
{ nullptr, nullptr, nullptr, nullptr},
@@ -414,8 +414,8 @@
StaticInstPtr
decodeSveStructStoreSSInsts(uint8_t esize, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex xn,
- IntRegIndex xm, int numregs)
+ RegIndex zt, RegIndex pg, RegIndex xn,
+ RegIndex xm, int numregs)
{
switch (esize) {
case 0:
@@ -436,7 +436,7 @@
StaticInstPtr
decodeSveGatherLoadVIInsts(uint8_t dtype, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex zn,
+ RegIndex zt, RegIndex pg, RegIndex zn,
uint64_t imm, bool esizeIs32,
bool firstFault)
{
@@ -526,8 +526,8 @@
StaticInstPtr
decodeSveGatherLoadSVInsts(uint8_t dtype, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg, IntRegIndex rn,
- IntRegIndex zm, bool esizeIs32, bool offsetIs32,
+ RegIndex zt, RegIndex pg, RegIndex rn,
+ RegIndex zm, bool esizeIs32, bool offsetIs32,
bool offsetIsSigned, bool offsetIsScaled,
bool firstFault)
{
@@ -629,8 +629,8 @@
StaticInstPtr
decodeSveScatterStoreVIInsts(uint8_t msz, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg,
- IntRegIndex zn, uint64_t imm,
+ RegIndex zt, RegIndex pg,
+ RegIndex zn, uint64_t imm,
bool esizeIs32)
{
const char* mn = "st1";
@@ -686,8 +686,8 @@
StaticInstPtr
decodeSveScatterStoreSVInsts(uint8_t msz, ExtMachInst machInst,
- IntRegIndex zt, IntRegIndex pg,
- IntRegIndex rn, IntRegIndex zm,
+ RegIndex zt, RegIndex pg,
+ RegIndex rn, RegIndex zm,
bool esizeIs32, bool offsetIs32,
bool offsetIsSigned, bool offsetIsScaled)
{
diff --git a/src/arch/arm/isa/operands.isa b/src/arch/arm/isa/operands.isa
index 6e3db63..7993ed2 100644
--- a/src/arch/arm/isa/operands.isa
+++ b/src/arch/arm/isa/operands.isa
@@ -111,14 +111,14 @@
@overrideInOperand
def makeRead(self):
'''Maybe PC read'''
- return f'{self.base_name} = ({self.reg_spec} == PCReg) ? ' \
+ return f'{self.base_name} = ({self.reg_spec} == int_reg::Pc) ? ' \
f'readPC(xc) : xc->getRegOperand(' \
f'this, {self.src_reg_idx});\n'
@overrideInOperand
def makeWrite(self):
'''Maybe PC write'''
return f'''
- if ({self.reg_spec} == PCReg)
+ if ({self.reg_spec} == int_reg::Pc)
setNextPC(xc, {self.base_name});
else
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
@@ -134,7 +134,7 @@
@overrideInOperand
def makeRead(self):
'''Maybe aligned PC read'''
- return f'{self.base_name} = ({self.reg_spec} == PCReg) ? ' \
+ return f'{self.base_name} = ({self.reg_spec} == int_reg::Pc) ? ' \
f'(roundDown(readPC(xc), 4)) : ' \
f'xc->getRegOperand(this, {self.src_reg_idx});\n'
@@ -143,7 +143,7 @@
def makeWrite(self):
'''Maybe interworking PC write'''
return f'''
- if ({self.reg_spec} == PCReg)
+ if ({self.reg_spec} == int_reg::Pc)
setIWNextPC(xc, {self.base_name});
else
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
@@ -156,7 +156,7 @@
def makeWrite(self):
'''Maybe aligned interworking PC write'''
return f'''
- if ({self.reg_spec} == PCReg) {"{"}
+ if ({self.reg_spec} == int_reg::Pc) {"{"}
if ((bool)THUMB)
setNextPC(xc, {self.base_name});
else
@@ -306,11 +306,12 @@
'PInt3': PIntReg('reg3'),
#Fixed index integer reg operands
- 'SpMode': IntRegNPC('intRegInMode((OperatingMode)regMode, INTREG_SP)'),
+ 'SpMode': IntRegNPC('int_reg::regInMode((OperatingMode)regMode, '
+ 'int_reg::Sp)'),
'DecodedBankedIntReg':
IntRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
- 'LR': IntRegNPC('INTREG_LR'),
- 'XLR': IntRegX64('INTREG_X30'),
+ 'LR': IntRegNPC('int_reg::Lr'),
+ 'XLR': IntRegX64('int_reg::X30'),
'R7': IntRegNPC('7'),
# First four arguments are passed in registers
'R0': IntRegNPC('0'),
diff --git a/src/arch/arm/isa/templates/branch.isa b/src/arch/arm/isa/templates/branch.isa
index b42a00f..b886a97 100644
--- a/src/arch/arm/isa/templates/branch.isa
+++ b/src/arch/arm/isa/templates/branch.isa
@@ -80,14 +80,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1,
ConditionCode _condCode);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template BranchRegCondConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1,
ConditionCode _condCode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _condCode)
{
@@ -114,7 +114,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2);
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
@@ -124,7 +124,7 @@
def template BranchRegRegConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
{
%(set_reg_idx_arr)s;
@@ -148,7 +148,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, int32_t imm, IntRegIndex _op1);
+ %(class_name)s(ExtMachInst machInst, int32_t imm, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
std::unique_ptr<PCStateBase> branchTarget(
const PCStateBase &branch_pc) const override;
@@ -162,7 +162,7 @@
// a register value even though the instruction is always unconditional.
def template BranchImmRegConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst, int32_t _imm,
- IntRegIndex _op1) :
+ RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
{
%(set_reg_idx_arr)s;
diff --git a/src/arch/arm/isa/templates/branch64.isa b/src/arch/arm/isa/templates/branch64.isa
index 5b38675..b3914e0 100644
--- a/src/arch/arm/isa/templates/branch64.isa
+++ b/src/arch/arm/isa/templates/branch64.isa
@@ -89,13 +89,13 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1);
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template BranchReg64Constructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
%(set_reg_idx_arr)s;
@@ -111,14 +111,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2);
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template BranchRegReg64Constructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
- IntRegIndex _op2) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1,
+ RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
{
%(set_reg_idx_arr)s;
@@ -134,14 +134,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, int64_t imm, IntRegIndex _op1);
+ %(class_name)s(ExtMachInst machInst, int64_t imm, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template BranchImmReg64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst, int64_t _imm,
- IntRegIndex _op1) :
+ RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _imm, _op1)
{
%(set_reg_idx_arr)s;
@@ -158,7 +158,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, int64_t _imm1, int64_t _imm2,
- IntRegIndex _op1);
+ RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
@@ -166,7 +166,7 @@
def template BranchImmImmReg64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
int64_t _imm1, int64_t _imm2,
- IntRegIndex _op1) :
+ RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_imm1, _imm2, _op1)
{
diff --git a/src/arch/arm/isa/templates/data64.isa b/src/arch/arm/isa/templates/data64.isa
index 2b1e8c4..69c4b64 100644
--- a/src/arch/arm/isa/templates/data64.isa
+++ b/src/arch/arm/isa/templates/data64.isa
@@ -43,15 +43,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataXImmConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
@@ -69,16 +69,16 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataXSRegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt,
ArmShiftType _shiftType) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -97,16 +97,16 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
ArmExtendType _extendType, int32_t _shiftAmt);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataXERegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
ArmExtendType _extendType,
int32_t _shiftAmt) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -125,14 +125,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataX1RegConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1) :
+ RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
%(set_reg_idx_arr)s;
@@ -148,15 +148,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataX2RegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
@@ -173,15 +173,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataX2RegImmConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
@@ -199,16 +199,16 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _op3);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataX3RegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _op3) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
+ RegIndex _op3) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _op3)
{
@@ -225,14 +225,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint64_t _imm, ConditionCode _condCode, uint8_t _defCc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataXCondCompImmConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint64_t _imm, ConditionCode _condCode,
uint8_t _defCc) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -251,15 +251,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
- IntRegIndex _op2, ConditionCode _condCode, uint8_t _defCc);
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1,
+ RegIndex _op2, ConditionCode _condCode, uint8_t _defCc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataXCondCompRegConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _op1, RegIndex _op2,
ConditionCode _condCode, uint8_t _defCc) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_op1, _op2, _condCode, _defCc)
@@ -277,16 +277,16 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
ConditionCode _condCode);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataXCondSelConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
ConditionCode _condCode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _condCode)
diff --git a/src/arch/arm/isa/templates/macromem.isa b/src/arch/arm/isa/templates/macromem.isa
index 094158a..dfda85c 100644
--- a/src/arch/arm/isa/templates/macromem.isa
+++ b/src/arch/arm/isa/templates/macromem.isa
@@ -166,18 +166,18 @@
public:
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _ura,
- IntRegIndex _urb,
- IntRegIndex _urc);
+ RegIndex _ura,
+ RegIndex _urb,
+ RegIndex _urc);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MicroSetPCCPSRConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _ura,
- IntRegIndex _urb,
- IntRegIndex _urc) :
+ RegIndex _ura,
+ RegIndex _urb,
+ RegIndex _urc) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_ura, _urb, _urc)
{
@@ -461,13 +461,13 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex rn, bool index, bool up,
+ %(class_name)s(ExtMachInst machInst, RegIndex rn, bool index, bool up,
bool user, bool writeback, bool load, uint32_t reglist);
};
}};
def template MacroMemConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
+%(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex rn,
bool index, bool up, bool user, bool writeback, bool load,
uint32_t reglist) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
@@ -493,13 +493,13 @@
public:
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
- bool load, IntRegIndex dest, IntRegIndex base, int64_t imm);
+ bool load, RegIndex dest, RegIndex base, int64_t imm);
};
}};
def template BigFpMemImmConstructor {{
%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
- bool load, IntRegIndex dest, IntRegIndex base, int64_t imm) :
+ bool load, RegIndex dest, RegIndex base, int64_t imm) :
%(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base, imm)
{
%(set_reg_idx_arr)s;
@@ -516,15 +516,15 @@
public:
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
- bool load, IntRegIndex dest, IntRegIndex base,
- IntRegIndex offset, ArmExtendType type, int64_t imm);
+ bool load, RegIndex dest, RegIndex base,
+ RegIndex offset, ArmExtendType type, int64_t imm);
};
}};
def template BigFpMemRegConstructor {{
%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
- bool load, IntRegIndex dest, IntRegIndex base,
- IntRegIndex offset, ArmExtendType type, int64_t imm) :
+ bool load, RegIndex dest, RegIndex base,
+ RegIndex offset, ArmExtendType type, int64_t imm) :
%(base_class)s(mnemonic, machInst, %(op_class)s, load, dest, base,
offset, type, imm)
{
@@ -542,13 +542,13 @@
public:
// Constructor
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
- IntRegIndex dest, int64_t imm);
+ RegIndex dest, int64_t imm);
};
}};
def template BigFpMemLitConstructor {{
%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
- IntRegIndex dest, int64_t imm) :
+ RegIndex dest, int64_t imm) :
%(base_class)s(mnemonic, machInst, %(op_class)s, dest, imm)
{
%(set_reg_idx_arr)s;
@@ -567,8 +567,8 @@
%(class_name)s(const char *mnemonic, ExtMachInst machInst,
uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
bool exclusive, bool acrel, uint32_t imm,
- AddrMode mode, IntRegIndex rn, IntRegIndex rt,
- IntRegIndex rt2);
+ AddrMode mode, RegIndex rn, RegIndex rt,
+ RegIndex rt2);
};
}};
@@ -576,7 +576,7 @@
%(class_name)s::%(class_name)s(const char *mnemonic, ExtMachInst machInst,
uint32_t size, bool fp, bool load, bool noAlloc, bool signExt,
bool exclusive, bool acrel, uint32_t imm, AddrMode mode,
- IntRegIndex rn, IntRegIndex rt, IntRegIndex rt2) :
+ RegIndex rn, RegIndex rt, RegIndex rt2) :
%(base_class)s(mnemonic, machInst, %(op_class)s, size,
fp, load, noAlloc, signExt, exclusive, acrel,
imm, mode, rn, rt, rt2)
@@ -659,14 +659,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex rn,
+ %(class_name)s(ExtMachInst machInst, RegIndex rn,
RegIndex vd, bool single, bool up, bool writeback,
bool load, uint32_t offset);
};
}};
def template MacroVFPMemConstructor {{
-%(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex rn,
+%(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex rn,
RegIndex vd, bool single, bool up, bool writeback, bool load,
uint32_t offset) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, rn,
diff --git a/src/arch/arm/isa/templates/mem.isa b/src/arch/arm/isa/templates/mem.isa
index 72e858f..35af775 100644
--- a/src/arch/arm/isa/templates/mem.isa
+++ b/src/arch/arm/isa/templates/mem.isa
@@ -875,7 +875,7 @@
%(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _base, int _mode, bool _wb) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_base, (AddrMode)_mode, _wb)
+ (RegIndex)_base, (AddrMode)_mode, _wb)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -931,7 +931,7 @@
%(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _op1, uint32_t _base) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_op1, (IntRegIndex)_base)
+ (RegIndex)_dest, (RegIndex)_op1, (RegIndex)_base)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -948,8 +948,8 @@
uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_dest2,
- (IntRegIndex)_base, _add, _imm)
+ (RegIndex)_dest, (RegIndex)_dest2,
+ (RegIndex)_base, _add, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -975,8 +975,8 @@
uint32_t _result, uint32_t _dest, uint32_t _dest2,
uint32_t _base, bool _add, int32_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_result, (IntRegIndex)_dest, (IntRegIndex)_dest2,
- (IntRegIndex)_base, _add, _imm)
+ (RegIndex)_result, (RegIndex)_dest, (RegIndex)_dest2,
+ (RegIndex)_base, _add, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1002,7 +1002,7 @@
%(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
+ (RegIndex)_dest, (RegIndex)_base, _add, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1028,8 +1028,8 @@
uint32_t _result, uint32_t _dest, uint32_t _base,
bool _add, int32_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_result, (IntRegIndex)_dest,
- (IntRegIndex)_base, _add, _imm)
+ (RegIndex)_result, (RegIndex)_dest,
+ (RegIndex)_base, _add, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1056,10 +1056,10 @@
uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_dest2,
- (IntRegIndex)_base, _add,
+ (RegIndex)_dest, (RegIndex)_dest2,
+ (RegIndex)_base, _add,
_shiftAmt, (ArmShiftType)_shiftType,
- (IntRegIndex)_index)
+ (RegIndex)_index)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1086,9 +1086,9 @@
uint32_t _dest, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_base, _add,
+ (RegIndex)_dest, (RegIndex)_base, _add,
_shiftAmt, (ArmShiftType)_shiftType,
- (IntRegIndex)_index)
+ (RegIndex)_index)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1115,10 +1115,10 @@
uint32_t _dest, uint32_t _dest2, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_dest2,
- (IntRegIndex)_base, _add,
+ (RegIndex)_dest, (RegIndex)_dest2,
+ (RegIndex)_base, _add,
_shiftAmt, (ArmShiftType)_shiftType,
- (IntRegIndex)_index)
+ (RegIndex)_index)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1131,8 +1131,8 @@
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
if ((_dest == _index) || (_dest2 == _index)) {
- IntRegIndex wbIndexReg = INTREG_UREG0;
- uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+ RegIndex wbIndexReg = int_reg::Ureg0;
+ uops[0] = new MicroUopRegMov(machInst, int_reg::Ureg0, _index);
uops[0]->setDelayedCommit();
uops[0]->setFirstMicroop();
uops[1] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
@@ -1141,7 +1141,7 @@
uops[2] = new %(wb_decl)s;
uops[2]->setLastMicroop();
} else {
- IntRegIndex wbIndexReg = index;
+ RegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, _dest, _dest2, _base, _add,
_shiftAmt, _shiftType, _index);
uops[0]->setDelayedCommit();
@@ -1158,9 +1158,9 @@
uint32_t _dest, uint32_t _base, bool _add,
int32_t _shiftAmt, uint32_t _shiftType, uint32_t _index) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_base, _add,
+ (RegIndex)_dest, (RegIndex)_base, _add,
_shiftAmt, (ArmShiftType)_shiftType,
- (IntRegIndex)_index)
+ (RegIndex)_index)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1174,15 +1174,16 @@
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
- if (_dest == INTREG_PC && !isFloating() && !isVector()) {
- IntRegIndex wbIndexReg = index;
- uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
+ if (_dest == int_reg::Pc && !isFloating() && !isVector()) {
+ RegIndex wbIndexReg = index;
+ uops[0] = new %(acc_name)s(machInst, int_reg::Ureg0, _base, _add,
_shiftAmt, _shiftType, _index);
uops[0]->setDelayedCommit();
uops[0]->setFirstMicroop();
uops[1] = new %(wb_decl)s;
uops[1]->setDelayedCommit();
- uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
+ uops[2] = new MicroUopRegMov(machInst, int_reg::Pc,
+ int_reg::Ureg0);
uops[2]->setFlag(StaticInst::IsControl);
uops[2]->setFlag(StaticInst::IsIndirectControl);
if (conditional)
@@ -1191,8 +1192,8 @@
uops[2]->setFlag(StaticInst::IsUncondControl);
uops[2]->setLastMicroop();
} else if(_dest == _index) {
- IntRegIndex wbIndexReg = INTREG_UREG0;
- uops[0] = new MicroUopRegMov(machInst, INTREG_UREG0, _index);
+ RegIndex wbIndexReg = int_reg::Ureg0;
+ uops[0] = new MicroUopRegMov(machInst, int_reg::Ureg0, _index);
uops[0]->setDelayedCommit();
uops[0]->setFirstMicroop();
uops[1] = new %(acc_name)s(machInst, _dest, _base, _add,
@@ -1201,7 +1202,7 @@
uops[2] = new %(wb_decl)s;
uops[2]->setLastMicroop();
} else {
- IntRegIndex wbIndexReg = index;
+ RegIndex wbIndexReg = index;
uops[0] = new %(acc_name)s(machInst, _dest, _base, _add,
_shiftAmt, _shiftType, _index);
uops[0]->setDelayedCommit();
@@ -1211,7 +1212,7 @@
}
#else
- if (_dest == INTREG_PC && !isFloating() && !isVector()) {
+ if (_dest == int_reg::Pc && !isFloating() && !isVector()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)
@@ -1227,7 +1228,7 @@
%(class_name)s::%(class_name)s(ExtMachInst machInst,
uint32_t _dest, uint32_t _base, bool _add, int32_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_base, _add, _imm)
+ (RegIndex)_dest, (RegIndex)_base, _add, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -1241,14 +1242,15 @@
#if %(use_uops)d
assert(numMicroops >= 2);
uops = new StaticInstPtr[numMicroops];
- if (_dest == INTREG_PC && !isFloating() && !isVector()) {
- uops[0] = new %(acc_name)s(machInst, INTREG_UREG0, _base, _add,
+ if (_dest == int_reg::Pc && !isFloating() && !isVector()) {
+ uops[0] = new %(acc_name)s(machInst, int_reg::Ureg0, _base, _add,
_imm);
uops[0]->setDelayedCommit();
uops[0]->setFirstMicroop();
uops[1] = new %(wb_decl)s;
uops[1]->setDelayedCommit();
- uops[2] = new MicroUopRegMov(machInst, INTREG_PC, INTREG_UREG0);
+ uops[2] = new MicroUopRegMov(
+ machInst, int_reg::Pc, int_reg::Ureg0);
uops[2]->setFlag(StaticInst::IsControl);
uops[2]->setFlag(StaticInst::IsIndirectControl);
/* Also set flags on the macroop so that pre-microop decomposition
@@ -1262,7 +1264,7 @@
uops[2]->setFlag(StaticInst::IsUncondControl);
setFlag(StaticInst::IsUncondControl);
}
- if (_base == INTREG_SP && _add && _imm == 4 && %(is_ras_pop)s) {
+ if (_base == int_reg::Sp && _add && _imm == 4 && %(is_ras_pop)s) {
uops[2]->setFlag(StaticInst::IsReturn);
setFlag(StaticInst::IsReturn);
}
@@ -1275,7 +1277,7 @@
uops[1]->setLastMicroop();
}
#else
- if (_dest == INTREG_PC && !isFloating() && !isVector()) {
+ if (_dest == int_reg::Pc && !isFloating() && !isVector()) {
flags[IsControl] = true;
flags[IsIndirectControl] = true;
if (conditional)
diff --git a/src/arch/arm/isa/templates/mem64.isa b/src/arch/arm/isa/templates/mem64.isa
index 444560a..5097fb0 100644
--- a/src/arch/arm/isa/templates/mem64.isa
+++ b/src/arch/arm/isa/templates/mem64.isa
@@ -290,7 +290,7 @@
public:
/// Constructor.
- %(class_name)s(ExtMachInst machInst, IntRegIndex _base,
+ %(class_name)s(ExtMachInst machInst, RegIndex _base,
MiscRegIndex _dest, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
@@ -307,7 +307,7 @@
}};
def template DCStore64Constructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _base,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _base,
MiscRegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_base, _dest, _imm)
@@ -385,7 +385,7 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, int64_t _imm);
+ RegIndex _dest, RegIndex _base, int64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
@@ -409,7 +409,7 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, int64_t _imm,
+ RegIndex _dest, RegIndex _base, int64_t _imm,
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
@@ -435,7 +435,7 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
+ RegIndex _dest, RegIndex _dest2, RegIndex _base,
int64_t _imm = 0, bool noAlloc = false, bool exclusive = false,
bool acrel = false);
@@ -464,8 +464,8 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, int64_t _imm = 0);
+ RegIndex _result, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, int64_t _imm = 0);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
@@ -484,7 +484,7 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
+ RegIndex _dest, RegIndex _base, RegIndex _offset,
ArmExtendType _type, uint32_t _shiftAmt);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
@@ -509,7 +509,7 @@
public:
/// Constructor.
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
+ RegIndex _dest, RegIndex _base, RegIndex _offset,
ArmExtendType _type, uint32_t _shiftAmt,
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
@@ -535,8 +535,8 @@
public:
/// Constructor.
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _base);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _base);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
@@ -559,8 +559,8 @@
public:
/// Constructor.
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _base, IntRegIndex _result);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _base, RegIndex _result);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
@@ -583,7 +583,7 @@
public:
/// Constructor.
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, int64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
@@ -606,7 +606,7 @@
public:
/// Constructor.
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, int64_t _imm,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, int64_t _imm,
bool noAlloc = false, bool exclusive = false,
bool acrel = false);
@@ -625,9 +625,9 @@
def template LoadStoreImm64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, int64_t _imm) :
+ RegIndex _dest, RegIndex _base, int64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, (IntRegIndex)_base, _imm)
+ (RegIndex)_dest, (RegIndex)_base, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -645,7 +645,7 @@
def template LoadStoreImmU64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, int64_t _imm,
+ RegIndex _dest, RegIndex _base, int64_t _imm,
bool noAlloc, bool exclusive, bool acrel) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _imm)
@@ -659,7 +659,7 @@
def template LoadStoreImmDU64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _dest2, IntRegIndex _base,
+ RegIndex _dest, RegIndex _dest2, RegIndex _base,
int64_t _imm, bool noAlloc, bool exclusive, bool acrel) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _dest2, _base, _imm)
@@ -673,8 +673,8 @@
def template StoreImmDEx64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _result, IntRegIndex _dest, IntRegIndex _dest2,
- IntRegIndex _base, int64_t _imm) :
+ RegIndex _result, RegIndex _dest, RegIndex _dest2,
+ RegIndex _base, int64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_result, _dest, _dest2, _base, _imm)
{
@@ -687,7 +687,7 @@
def template LoadStoreReg64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
+ RegIndex _dest, RegIndex _base, RegIndex _offset,
ArmExtendType _type, uint32_t _shiftAmt) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _offset, _type, _shiftAmt)
@@ -709,7 +709,7 @@
def template LoadStoreRegU64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
+ RegIndex _dest, RegIndex _base, RegIndex _offset,
ArmExtendType _type, uint32_t _shiftAmt,
bool noAlloc, bool exclusive, bool acrel) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -724,7 +724,7 @@
def template LoadStoreRaw64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base) :
+ RegIndex _dest, RegIndex _base) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _base)
{
%(set_reg_idx_arr)s;
@@ -734,7 +734,7 @@
def template LoadStoreEx64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result) :
+ RegIndex _dest, RegIndex _base, RegIndex _result) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _result)
{
@@ -745,9 +745,9 @@
def template LoadStoreLit64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, int64_t _imm) :
+ RegIndex _dest, int64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, _imm)
+ (RegIndex)_dest, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -765,10 +765,10 @@
def template LoadStoreLitU64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, int64_t _imm,
+ RegIndex _dest, int64_t _imm,
bool noAlloc, bool exclusive, bool acrel) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
- (IntRegIndex)_dest, _imm)
+ (RegIndex)_dest, _imm)
{
%(set_reg_idx_arr)s;
%(constructor)s;
@@ -859,8 +859,8 @@
public:
/// Constructor.
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _base, IntRegIndex _result);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _base, RegIndex _result);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
@@ -878,7 +878,7 @@
def template AmoOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result) :
+ RegIndex _dest, RegIndex _base, RegIndex _result) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _result)
{
@@ -898,8 +898,8 @@
public:
bool isXZR ;
/// Constructor.
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _base, IntRegIndex _result);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _base, RegIndex _result);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
@@ -916,7 +916,7 @@
def template AmoArithmeticOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _result) :
+ RegIndex _dest, RegIndex _base, RegIndex _result) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _result)
{
diff --git a/src/arch/arm/isa/templates/misc.isa b/src/arch/arm/isa/templates/misc.isa
index 3d3393d..36c78f6 100644
--- a/src/arch/arm/isa/templates/misc.isa
+++ b/src/arch/arm/isa/templates/misc.isa
@@ -43,13 +43,13 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MrsConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
%(set_reg_idx_arr)s;
@@ -74,14 +74,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint8_t _sysM, bool _r);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MrsBankedRegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint8_t _sysM, bool _r) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest),
byteMask(_sysM), r(_r)
@@ -107,14 +107,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint8_t _sysM, bool _r);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MsrBankedRegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint8_t _sysM, bool _r) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _sysM),
r(_r)
@@ -137,13 +137,13 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, uint8_t mask);
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1, uint8_t mask);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MsrRegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _op1,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _op1,
uint8_t mask) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, mask)
{
@@ -194,14 +194,14 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _op1,
- IntRegIndex _dest, IntRegIndex _dest2, uint32_t imm);
+ RegIndex _dest, RegIndex _dest2, uint32_t imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template MrrcOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex op1,
- IntRegIndex dest, IntRegIndex dest2,
+ RegIndex dest, RegIndex dest2,
uint32_t imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, dest,
dest2, imm)
@@ -224,15 +224,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2,
MiscRegIndex _dest, uint32_t imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template McrrOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex op1,
- IntRegIndex op2, MiscRegIndex dest,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex op1,
+ RegIndex op2, MiscRegIndex dest,
uint32_t imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, op1, op2,
dest, imm)
@@ -282,14 +282,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegImmOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, uint64_t _imm) :
+ RegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
%(set_reg_idx_arr)s;
@@ -310,14 +310,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegRegOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1) :
+ RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
%(set_reg_idx_arr)s;
@@ -338,15 +338,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegRegRegImmOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
@@ -369,16 +369,16 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _op3);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _op3);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegRegRegRegOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _op3) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
+ RegIndex _op3) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _op3)
{
@@ -400,15 +400,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegRegRegOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
@@ -430,15 +430,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegRegImmOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
@@ -460,7 +460,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, MiscRegIndex _dest, RegIndex _op1,
uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -468,7 +468,7 @@
def template MiscRegRegImmOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
@@ -490,14 +490,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, MiscRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, MiscRegIndex _op1,
uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegMiscRegImmOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
MiscRegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
@@ -520,14 +520,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm1, uint64_t _imm2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegImmImmOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm1, uint64_t _imm2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm1, _imm2)
@@ -550,7 +550,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -558,7 +558,7 @@
def template RegRegImmImmOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm1, _imm2)
@@ -581,15 +581,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- uint64_t _imm, IntRegIndex _op1);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ uint64_t _imm, RegIndex _op1);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegImmRegOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- uint64_t _imm, IntRegIndex _op1) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ uint64_t _imm, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _op1)
{
@@ -611,16 +611,16 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm,
- IntRegIndex _op1, int32_t _shiftAmt,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm,
+ RegIndex _op1, int32_t _shiftAmt,
ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegImmRegShiftOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- uint64_t _imm, IntRegIndex _op1,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ uint64_t _imm, RegIndex _op1,
int32_t _shiftAmt,
ArmShiftType _shiftType) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -645,7 +645,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm);
+ RegIndex _op1, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
diff --git a/src/arch/arm/isa/templates/misc64.isa b/src/arch/arm/isa/templates/misc64.isa
index fd44976..7c15c39 100644
--- a/src/arch/arm/isa/templates/misc64.isa
+++ b/src/arch/arm/isa/templates/misc64.isa
@@ -67,7 +67,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -75,7 +75,7 @@
def template RegRegImmImmOp64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
uint64_t _imm1, uint64_t _imm2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm1, _imm2)
@@ -93,15 +93,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1,
- IntRegIndex _op2, uint64_t _imm);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
+ RegIndex _op2, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template RegRegRegImmOp64Constructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
@@ -144,7 +144,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm);
+ RegIndex _op1, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -152,7 +152,7 @@
def template MiscRegRegOp64Constructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
@@ -169,7 +169,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
MiscRegIndex _op1, uint64_t _imm);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
@@ -177,7 +177,7 @@
}};
def template RegMiscRegOp64Constructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
MiscRegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
@@ -196,13 +196,13 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template XPauthOpRegRegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
%(set_reg_idx_arr)s;
@@ -219,14 +219,14 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest);
Fault execute(ExecContext *, Trace::InstRecord *) const;
};
}};
def template RegNoneConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
%(set_reg_idx_arr)s;
@@ -244,7 +244,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm, bool dvm_enabled);
+ RegIndex _op1, uint64_t _imm, bool dvm_enabled);
Fault initiateAcc(ExecContext *, Trace::InstRecord *) const override;
Fault completeAcc(PacketPtr, ExecContext *,
@@ -275,7 +275,7 @@
def template DvmTlbiConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst, MiscRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm,
+ RegIndex _op1, uint64_t _imm,
bool dvm_enabled) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm),
diff --git a/src/arch/arm/isa/templates/mult.isa b/src/arch/arm/isa/templates/mult.isa
index f30bc79..e94cc93 100644
--- a/src/arch/arm/isa/templates/mult.isa
+++ b/src/arch/arm/isa/templates/mult.isa
@@ -43,15 +43,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _reg0,
- IntRegIndex _reg1, IntRegIndex _reg2);
+ %(class_name)s(ExtMachInst machInst, RegIndex _reg0,
+ RegIndex _reg1, RegIndex _reg2);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template Mult3Constructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0,
- IntRegIndex _reg1, IntRegIndex _reg2) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _reg0,
+ RegIndex _reg1, RegIndex _reg2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_reg0, _reg1, _reg2)
{
@@ -74,16 +74,16 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _reg0, IntRegIndex _reg1,
- IntRegIndex _reg2, IntRegIndex _reg3);
+ RegIndex _reg0, RegIndex _reg1,
+ RegIndex _reg2, RegIndex _reg3);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template Mult4Constructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _reg0,
- IntRegIndex _reg1, IntRegIndex _reg2,
- IntRegIndex _reg3) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _reg0,
+ RegIndex _reg1, RegIndex _reg2,
+ RegIndex _reg3) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_reg0, _reg1, _reg2, _reg3)
{
diff --git a/src/arch/arm/isa/templates/neon.isa b/src/arch/arm/isa/templates/neon.isa
index 7e9b2b1..2a64424 100644
--- a/src/arch/arm/isa/templates/neon.isa
+++ b/src/arch/arm/isa/templates/neon.isa
@@ -61,7 +61,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
@@ -91,7 +91,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
@@ -122,7 +122,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _dest, RegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
@@ -151,7 +151,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
%(set_reg_idx_arr)s;
@@ -180,7 +180,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1) :
+ RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1)
{
diff --git a/src/arch/arm/isa/templates/neon64.isa b/src/arch/arm/isa/templates/neon64.isa
index f19f89d..f315f1e 100644
--- a/src/arch/arm/isa/templates/neon64.isa
+++ b/src/arch/arm/isa/templates/neon64.isa
@@ -52,7 +52,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
@@ -77,7 +77,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
@@ -102,7 +102,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
%(set_reg_idx_arr)s;
@@ -126,7 +126,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm) :
+ RegIndex _dest, RegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
@@ -151,7 +151,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm1,
+ RegIndex _dest, RegIndex _op1, uint64_t _imm1,
uint64_t _imm2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm1, _imm2)
@@ -176,7 +176,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
%(set_reg_idx_arr)s;
diff --git a/src/arch/arm/isa/templates/pred.isa b/src/arch/arm/isa/templates/pred.isa
index b461aaf..3acc724 100644
--- a/src/arch/arm/isa/templates/pred.isa
+++ b/src/arch/arm/isa/templates/pred.isa
@@ -56,15 +56,15 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint32_t _imm, bool _rotC=true);
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, uint32_t _imm, bool _rotC=true);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataImmConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint32_t _imm,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, uint32_t _imm,
bool _rotC) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm, _rotC)
@@ -96,16 +96,16 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt, ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataRegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
int32_t _shiftAmt,
ArmShiftType _shiftType) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -143,17 +143,17 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _shift,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _shift,
ArmShiftType _shiftType);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template DataRegRegConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _shift,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
+ RegIndex _shift,
ArmShiftType _shiftType) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _shift, _shiftType)
diff --git a/src/arch/arm/isa/templates/sve.isa b/src/arch/arm/isa/templates/sve.isa
index cf77b71..b52a189 100644
--- a/src/arch/arm/isa/templates/sve.isa
+++ b/src/arch/arm/isa/templates/sve.isa
@@ -61,7 +61,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
@@ -87,7 +87,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op1, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
@@ -112,7 +112,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
%(set_reg_idx_arr)s;
@@ -136,7 +136,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, %(isSimdFp)s)
{
@@ -161,7 +161,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint64_t _imm) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
%(set_reg_idx_arr)s;
@@ -186,7 +186,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp,
+ RegIndex _dest, uint64_t _imm, RegIndex _gp,
bool _isMerging=true) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _gp, _isMerging)
@@ -213,7 +213,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, uint64_t _imm)
+ RegIndex _dest, RegIndex _op1, uint64_t _imm)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
@@ -239,7 +239,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, uint64_t _imm, IntRegIndex _gp) :
+ RegIndex _dest, uint64_t _imm, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _gp)
{
@@ -265,7 +265,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op2, IntRegIndex _gp) :
+ RegIndex _dest, RegIndex _op2, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op2, _gp)
{
@@ -291,8 +291,8 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _gp, SvePredType _predType) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _gp, SvePredType _predType) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, _predType)
{
@@ -318,7 +318,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
@@ -343,8 +343,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, uint8_t _index) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, uint8_t _index) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _index)
{
@@ -370,8 +370,8 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _gp, bool _isSel=false) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _gp, bool _isSel=false) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, _isSel)
{
@@ -396,8 +396,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp)
{
@@ -422,8 +422,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, %(op2IsWide)s)
{
@@ -448,8 +448,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm, _gp)
{
@@ -474,8 +474,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp)
{
@@ -500,8 +500,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm)
{
@@ -526,8 +526,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
@@ -555,8 +555,8 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
@@ -581,7 +581,7 @@
public:
// Constructor
- SveIndexII(ExtMachInst machInst, IntRegIndex _dest,
+ SveIndexII(ExtMachInst machInst, RegIndex _dest,
int8_t _imm1, int8_t _imm2) :
SveIndexIIOp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm1, _imm2)
@@ -607,8 +607,8 @@
public:
// Constructor
- SveIndexIR(ExtMachInst machInst, IntRegIndex _dest,
- int8_t _imm, IntRegIndex _op) :
+ SveIndexIR(ExtMachInst machInst, RegIndex _dest,
+ int8_t _imm, RegIndex _op) :
SveIndexIROp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, _op)
{
@@ -633,8 +633,8 @@
public:
// Constructor
- SveIndexRI(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op, int8_t _imm) :
+ SveIndexRI(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op, int8_t _imm) :
SveIndexRIOp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op, _imm)
{
@@ -659,8 +659,8 @@
public:
// Constructor
- SveIndexRR(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2) :
+ SveIndexRR(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2) :
SveIndexRROp("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
@@ -684,7 +684,7 @@
typedef _Element TPElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, %(srcIs32b)s, %(destIsVec)s)
{
@@ -708,8 +708,8 @@
typedef _Element TPElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _gp)
{
@@ -735,7 +735,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, uint8_t _imm) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, uint8_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _imm)
{
%(set_reg_idx_arr)s;
@@ -760,7 +760,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, IntRegIndex _offset,
+ RegIndex _dest, RegIndex _base, RegIndex _offset,
uint8_t _mult, SveAdrOffsetFormat _offsetFormat) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _offset, _mult, _offsetFormat)
@@ -785,8 +785,8 @@
typedef _Element TPElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, %(srcIs32b)s)
{
@@ -810,7 +810,7 @@
typedef _Element TPElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _op2) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _op2)
{
%(set_reg_idx_arr)s;
@@ -833,8 +833,8 @@
typedef _Element TPElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1,
- int64_t _op2, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1,
+ int64_t _op2, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1,
_op2, _gp)
{
@@ -858,7 +858,7 @@
typedef _Element TPElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint8_t _pattern, uint8_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_pattern, _imm, %(dstIsVec)s, %(dstIs32b)s)
@@ -879,8 +879,8 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _gp,
- IntRegIndex _op1) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _gp,
+ RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_gp, _op1, %(isMerging)s)
{
@@ -901,8 +901,8 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_op1, _op2, _gp)
{
@@ -926,8 +926,8 @@
typedef _Element TPElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest,
_op1, _gp, %(isCond)s, %(isScalar)s, %(isSimdFp)s)
{
@@ -955,7 +955,7 @@
typedef _DElement TPDElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _op1) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _op1)
{
%(set_reg_idx_arr)s;
@@ -973,7 +973,7 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1, _gp)
{
%(set_reg_idx_arr)s;
@@ -991,7 +991,7 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest)
{
%(set_reg_idx_arr)s;
@@ -1009,7 +1009,7 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest, IntRegIndex _gp) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest, RegIndex _gp) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _dest, _gp)
{
%(set_reg_idx_arr)s;
@@ -1027,7 +1027,7 @@
%(reg_idx_arr_decl)s;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _op1) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _op1) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s, _op1)
{
%(set_reg_idx_arr)s;
@@ -1071,8 +1071,8 @@
typedef _DElement TPDElem;
public:
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2, uint64_t _imm) :
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _imm)
{
@@ -1101,7 +1101,7 @@
public:
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2)
{
@@ -1128,8 +1128,8 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _gp, uint8_t _rot) :
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _gp, uint8_t _rot) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _gp, _rot)
{
@@ -1155,7 +1155,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
uint8_t _rot, uint8_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _rot, _imm)
diff --git a/src/arch/arm/isa/templates/sve_mem.isa b/src/arch/arm/isa/templates/sve_mem.isa
index 017ace8..5eb8975 100644
--- a/src/arch/arm/isa/templates/sve_mem.isa
+++ b/src/arch/arm/isa/templates/sve_mem.isa
@@ -46,7 +46,7 @@
public:
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _base, uint64_t _imm) :
+ RegIndex _dest, RegIndex _base, uint64_t _imm) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _base, _imm)
{
@@ -79,8 +79,8 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
- IntRegIndex _offset) :
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
+ RegIndex _offset) :
%(base_class)s(mnem, machInst, %(op_class)s,
_dest, _gp, _base, _offset)
{
@@ -113,7 +113,7 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
uint64_t _imm) :
%(base_class)s(mnem, machInst, %(op_class)s,
_dest, _gp, _base, _imm)
@@ -418,9 +418,9 @@
protected:
typedef RegElemType TPElem;
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
uint64_t imm;
int elemIndex;
@@ -431,8 +431,8 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp,
- IntRegIndex _base, uint64_t _imm, int _elemIndex,
+ OpClass __opClass, RegIndex _dest, RegIndex _gp,
+ RegIndex _base, uint64_t _imm, int _elemIndex,
int _numElems, bool _firstFault) :
%(base_class)s(mnem, machInst, %(op_class)s),
dest(_dest), gp(_gp), base(_base), imm(_imm),
@@ -500,10 +500,10 @@
protected:
typedef RegElemType TPElem;
- IntRegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
- IntRegIndex offset;
+ RegIndex dest;
+ RegIndex gp;
+ RegIndex base;
+ RegIndex offset;
bool offsetIs32;
bool offsetIsSigned;
@@ -517,8 +517,8 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- OpClass __opClass, IntRegIndex _dest, IntRegIndex _gp,
- IntRegIndex _base, IntRegIndex _offset, bool _offsetIs32,
+ OpClass __opClass, RegIndex _dest, RegIndex _gp,
+ RegIndex _base, RegIndex _offset, bool _offsetIs32,
bool _offsetIsSigned, bool _offsetIsScaled, int _elemIndex,
int _numElems, bool _firstFault) :
%(base_class)s(mnem, machInst, %(op_class)s),
@@ -834,13 +834,13 @@
%(reg_idx_arr_decl)s;
protected:
- IntRegIndex op1;
+ RegIndex op1;
StaticInst *macroOp;
public:
SveGatherLoadCpySrcVecMicroop(const char* mnem, ExtMachInst machInst,
- IntRegIndex _op1, StaticInst *_macroOp) :
+ RegIndex _op1, StaticInst *_macroOp) :
MicroOp(mnem, machInst, SimdAluOp), op1(_op1), macroOp(_macroOp)
{
%(set_reg_idx_arr)s;
@@ -891,8 +891,8 @@
typedef _Element TPElem;
RegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
+ RegIndex gp;
+ RegIndex base;
int64_t imm;
uint8_t numRegs;
@@ -904,7 +904,7 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- RegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
int64_t _imm, uint8_t _numRegs, int _regIndex) :
%(base_class)s(mnem, machInst, %(op_class)s),
dest(_dest), gp(_gp), base(_base), imm(_imm),
@@ -1168,9 +1168,9 @@
typedef _Element TPElem;
RegIndex dest;
- IntRegIndex gp;
- IntRegIndex base;
- IntRegIndex offset;
+ RegIndex gp;
+ RegIndex base;
+ RegIndex offset;
uint8_t numRegs;
int regIndex;
@@ -1181,8 +1181,8 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- RegIndex _dest, IntRegIndex _gp, IntRegIndex _base,
- IntRegIndex _offset, uint8_t _numRegs, int _regIndex) :
+ RegIndex _dest, RegIndex _gp, RegIndex _base,
+ RegIndex _offset, uint8_t _numRegs, int _regIndex) :
%(base_class)s(mnem, machInst, %(op_class)s),
dest(_dest), gp(_gp), base(_base), offset(_offset),
numRegs(_numRegs), regIndex(_regIndex),
@@ -1253,8 +1253,8 @@
protected:
typedef _Element Element;
typedef _Element TPElem;
- IntRegIndex dest;
- IntRegIndex op1;
+ RegIndex dest;
+ RegIndex op1;
uint8_t numRegs;
int regIndex;
@@ -1262,7 +1262,7 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
uint8_t _numRegs, int _regIndex, StaticInst *_macroOp) :
MicroOp(mnem, machInst, SimdAluOp), dest(_dest), op1(_op1),
numRegs(_numRegs), regIndex(_regIndex), macroOp(_macroOp)
@@ -1295,7 +1295,7 @@
protected:
typedef _Element Element;
typedef _Element TPElem;
- IntRegIndex dest;
+ RegIndex dest;
uint8_t numRegs;
int regIndex;
@@ -1303,7 +1303,7 @@
public:
%(class_name)s(const char* mnem, ExtMachInst machInst,
- IntRegIndex _dest, uint8_t _numRegs, int _regIndex,
+ RegIndex _dest, uint8_t _numRegs, int _regIndex,
StaticInst *_macroOp) :
MicroOp(mnem, machInst, SimdAluOp), dest(_dest),
numRegs(_numRegs), regIndex(_regIndex), macroOp(_macroOp)
diff --git a/src/arch/arm/isa/templates/vfp.isa b/src/arch/arm/isa/templates/vfp.isa
index 26303cb..2f59f4f 100644
--- a/src/arch/arm/isa/templates/vfp.isa
+++ b/src/arch/arm/isa/templates/vfp.isa
@@ -104,7 +104,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -112,7 +112,7 @@
def template FpRegRegOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, mode)
@@ -135,7 +135,7 @@
public:
// Constructor
- %(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
+ %(class_name)s(ExtMachInst machInst, RegIndex _dest,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -143,7 +143,7 @@
def template FpRegImmOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode)
+ RegIndex _dest, uint64_t _imm, VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, mode)
{
@@ -166,7 +166,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
uint64_t _imm, VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -174,8 +174,8 @@
def template FpRegRegImmOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest,
- IntRegIndex _op1,
+ RegIndex _dest,
+ RegIndex _op1,
uint64_t _imm,
VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
@@ -200,7 +200,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
@@ -208,9 +208,9 @@
def template FpRegRegRegOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest,
- IntRegIndex _op1,
- IntRegIndex _op2,
+ RegIndex _dest,
+ RegIndex _op1,
+ RegIndex _op2,
VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, mode)
@@ -234,7 +234,7 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
ConditionCode _cond,
VfpMicroMode mode = VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
@@ -243,9 +243,9 @@
def template FpRegRegRegCondOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest,
- IntRegIndex _op1,
- IntRegIndex _op2,
+ RegIndex _dest,
+ RegIndex _op1,
+ RegIndex _op2,
ConditionCode _cond,
VfpMicroMode mode)
: %(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
diff --git a/src/arch/arm/isa/templates/vfp64.isa b/src/arch/arm/isa/templates/vfp64.isa
index 2548940..883fd43 100644
--- a/src/arch/arm/isa/templates/vfp64.isa
+++ b/src/arch/arm/isa/templates/vfp64.isa
@@ -37,7 +37,7 @@
def template AA64FpRegRegOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1,
+ RegIndex _dest, RegIndex _op1,
VfpMicroMode mode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, mode)
@@ -49,7 +49,7 @@
def template AA64FpRegImmOpConstructor {{
%(class_name)s::%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, uint64_t _imm, VfpMicroMode mode) :
+ RegIndex _dest, uint64_t _imm, VfpMicroMode mode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _imm, mode)
{
@@ -59,8 +59,8 @@
}};
def template AA64FpRegRegImmOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, uint64_t _imm,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, uint64_t _imm,
VfpMicroMode mode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _imm, mode)
@@ -71,8 +71,8 @@
}};
def template AA64FpRegRegRegOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
VfpMicroMode mode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, mode)
@@ -91,16 +91,16 @@
public:
// Constructor
%(class_name)s(ExtMachInst machInst,
- IntRegIndex _dest, IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _op3, VfpMicroMode mode=VfpNotAMicroop);
+ RegIndex _dest, RegIndex _op1, RegIndex _op2,
+ RegIndex _op3, VfpMicroMode mode=VfpNotAMicroop);
Fault execute(ExecContext *, Trace::InstRecord *) const override;
};
}};
def template AA64FpRegRegRegRegOpConstructor {{
- %(class_name)s::%(class_name)s(ExtMachInst machInst, IntRegIndex _dest,
- IntRegIndex _op1, IntRegIndex _op2,
- IntRegIndex _op3, VfpMicroMode mode) :
+ %(class_name)s::%(class_name)s(ExtMachInst machInst, RegIndex _dest,
+ RegIndex _op1, RegIndex _op2,
+ RegIndex _op3, VfpMicroMode mode) :
%(base_class)s("%(mnemonic)s", machInst, %(op_class)s,
_dest, _op1, _op2, _op3, mode)
{
diff --git a/src/arch/arm/kvm/arm_cpu.cc b/src/arch/arm/kvm/arm_cpu.cc
index 33237c9..becb6b9 100644
--- a/src/arch/arm/kvm/arm_cpu.cc
+++ b/src/arch/arm/kvm/arm_cpu.cc
@@ -191,7 +191,7 @@
}
constexpr KvmIntRegInfo
-regCore32(off_t offset, ArmISA::IntRegIndex idx, const char *name)
+regCore32(off_t offset, RegIndex idx, const char *name)
{
return { KVM_REG_ARM | KVM_REG_SIZE_U32 | KVM_REG_ARM_CORE | offset,
idx, name };
@@ -285,43 +285,43 @@
ArmKvmCPU::KvmIntRegInfo ArmKvmCPU::kvmIntRegs[] = {
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r0), INTREG_R0, "R0"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r1), INTREG_R1, "R1"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r2), INTREG_R2, "R2"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r3), INTREG_R3, "R3"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r4), INTREG_R4, "R4"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r5), INTREG_R5, "R5"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r6), INTREG_R6, "R6"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r7), INTREG_R7, "R7"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r8), INTREG_R8, "R8"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r9), INTREG_R9, "R9"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r10), INTREG_R10, "R10"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_fp), INTREG_R11, "R11"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_ip), INTREG_R12, "R12"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_sp), INTREG_R13, "R13(USR)"),
- regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_lr), INTREG_R14, "R14(USR)"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r0), int_reg::R0, "R0"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r1), int_reg::R1, "R1"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r2), int_reg::R2, "R2"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r3), int_reg::R3, "R3"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r4), int_reg::R4, "R4"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r5), int_reg::R5, "R5"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r6), int_reg::R6, "R6"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r7), int_reg::R7, "R7"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r8), int_reg::R8, "R8"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r9), int_reg::R9, "R9"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_r10), int_reg::R10, "R10"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_fp), int_reg::R11, "R11"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_ip), int_reg::R12, "R12"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_sp), int_reg::R13, "R13(USR)"),
+ regCore32(KVM_REG_ARM_CORE_REG(usr_regs.ARM_lr), int_reg::R14, "R14(USR)"),
- regCore32(KVM_REG_ARM_CORE_REG(svc_regs[0]), INTREG_SP_SVC, "R13(SVC)"),
- regCore32(KVM_REG_ARM_CORE_REG(svc_regs[1]), INTREG_LR_SVC, "R14(SVC)"),
+ regCore32(KVM_REG_ARM_CORE_REG(svc_regs[0]), int_reg::SpSvc, "R13(SVC)"),
+ regCore32(KVM_REG_ARM_CORE_REG(svc_regs[1]), int_reg::LrSvc, "R14(SVC)"),
- regCore32(KVM_REG_ARM_CORE_REG(abt_regs[0]), INTREG_SP_ABT, "R13(ABT)"),
- regCore32(KVM_REG_ARM_CORE_REG(abt_regs[1]), INTREG_LR_ABT, "R14(ABT)"),
+ regCore32(KVM_REG_ARM_CORE_REG(abt_regs[0]), int_reg::SpAbt, "R13(ABT)"),
+ regCore32(KVM_REG_ARM_CORE_REG(abt_regs[1]), int_reg::LrAbt, "R14(ABT)"),
- regCore32(KVM_REG_ARM_CORE_REG(und_regs[0]), INTREG_SP_UND, "R13(UND)"),
- regCore32(KVM_REG_ARM_CORE_REG(und_regs[1]), INTREG_LR_UND, "R14(UND)"),
+ regCore32(KVM_REG_ARM_CORE_REG(und_regs[0]), int_reg::SpUnd, "R13(UND)"),
+ regCore32(KVM_REG_ARM_CORE_REG(und_regs[1]), int_reg::LrUnd, "R14(UND)"),
- regCore32(KVM_REG_ARM_CORE_REG(irq_regs[0]), INTREG_SP_IRQ, "R13(IRQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(irq_regs[1]), INTREG_LR_IRQ, "R14(IRQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(irq_regs[0]), int_reg::SpIrq, "R13(IRQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(irq_regs[1]), int_reg::LrIrq, "R14(IRQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[0]), INTREG_R8_FIQ, "R8(FIQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[1]), INTREG_R9_FIQ, "R9(FIQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[2]), INTREG_R10_FIQ, "R10(FIQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[3]), INTREG_R11_FIQ, "R11(FIQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[4]), INTREG_R12_FIQ, "R12(FIQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[5]), INTREG_R13_FIQ, "R13(FIQ)"),
- regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[6]), INTREG_R14_FIQ, "R14(FIQ)"),
- { 0, NUM_INTREGS, NULL }
+ regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[0]), int_reg::R8Fiq, "R8(FIQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[1]), int_reg::R9Fiq, "R9(FIQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[2]), int_reg::R10Fiq, "R10(FIQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[3]), int_reg::R11Fiq, "R11(FIQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[4]), int_reg::R12Fiq, "R12(FIQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[5]), int_reg::R13Fiq, "R13(FIQ)"),
+ regCore32(KVM_REG_ARM_CORE_REG(fiq_regs[6]), int_reg::R14Fiq, "R14(FIQ)"),
+ { 0, int_reg::NumRegs, NULL }
};
ArmKvmCPU::KvmCoreMiscRegInfo ArmKvmCPU::kvmCoreMiscRegs[] = {
@@ -545,7 +545,7 @@
inform("PC: 0x%x\n", pc);
for (const KvmIntRegInfo *ri(kvmIntRegs);
- ri->idx != NUM_INTREGS; ++ri) {
+ ri->idx != int_reg::NumRegs; ++ri) {
uint32_t value(getOneRegU32(ri->id));
inform("%s: 0x%x\n", ri->name, value);
@@ -662,9 +662,9 @@
ArmKvmCPU::updateKvmStateCore()
{
for (const KvmIntRegInfo *ri(kvmIntRegs);
- ri->idx != NUM_INTREGS; ++ri) {
+ ri->idx != init_reg::NumRegs; ++ri) {
- uint64_t value = tc->readIntRegFlat(ri->idx);
+ uint64_t value = tc->getRegFlat(RegId(IntRegClass, ri->idx));
DPRINTF(KvmContext, "kvm(%s) := 0x%x\n", ri->name, value);
setOneReg(ri->id, value);
}
@@ -802,9 +802,9 @@
ArmKvmCPU::updateTCStateCore()
{
for (const KvmIntRegInfo *ri(kvmIntRegs);
- ri->idx != NUM_INTREGS; ++ri) {
+ ri->idx != int_reg::NumRegs; ++ri) {
- tc->setIntRegFlat(ri->idx, getOneRegU32(ri->id));
+ tc->setRegFlat(RegId(IntRegClass, ri->idx), getOneRegU32(ri->id));
}
for (const KvmCoreMiscRegInfo *ri(kvmCoreMiscRegs);
diff --git a/src/arch/arm/kvm/arm_cpu.hh b/src/arch/arm/kvm/arm_cpu.hh
index a16a095..849aa76 100644
--- a/src/arch/arm/kvm/arm_cpu.hh
+++ b/src/arch/arm/kvm/arm_cpu.hh
@@ -76,7 +76,7 @@
/** KVM ID */
const uint64_t id;
/** gem5 index */
- const ArmISA::IntRegIndex idx;
+ const RegIndex idx;
/** Name in debug output */
const char *name;
};
diff --git a/src/arch/arm/kvm/armv8_cpu.cc b/src/arch/arm/kvm/armv8_cpu.cc
index 937b9c6..328a39e 100644
--- a/src/arch/arm/kvm/armv8_cpu.cc
+++ b/src/arch/arm/kvm/armv8_cpu.cc
@@ -49,7 +49,7 @@
// Unlike gem5, kvm doesn't count the SP as a normal integer register,
// which means we only have 31 normal integer registers.
-constexpr static unsigned NUM_XREGS = NUM_ARCH_INTREGS - 1;
+constexpr static unsigned NUM_XREGS = int_reg::NumArchRegs - 1;
static_assert(NUM_XREGS == 31, "Unexpected number of aarch64 int. regs.");
// The KVM interface accesses vector registers of 4 single precision
@@ -104,8 +104,8 @@
#define FP_REGS_PER_VFP_REG 4
const std::vector<ArmV8KvmCPU::IntRegInfo> ArmV8KvmCPU::intRegMap = {
- { INT_REG(regs.sp), INTREG_SP0, "SP(EL0)" },
- { INT_REG(sp_el1), INTREG_SP1, "SP(EL1)" },
+ { INT_REG(regs.sp), int_reg::Sp0, "SP(EL0)" },
+ { INT_REG(sp_el1), int_reg::Sp1, "SP(EL1)" },
};
const std::vector<ArmV8KvmCPU::MiscRegInfo> ArmV8KvmCPU::miscRegMap = {
@@ -243,13 +243,13 @@
}
for (int i = 0; i < NUM_XREGS; ++i) {
- const uint64_t value(tc->readIntReg(INTREG_X0 + i));
+ const uint64_t value = tc->getReg(int_reg::x(i));
DPRINTF(KvmContext, " X%i := 0x%x\n", i, value);
setOneReg(kvmXReg(i), value);
}
for (const auto &ri : intRegMap) {
- const uint64_t value(tc->readIntReg(ri.idx));
+ const uint64_t value = tc->getReg(RegId(IntRegClass, ri.idx));
DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
setOneReg(ri.kvm, value);
}
@@ -316,16 +316,16 @@
// KVM64 returns registers in 64-bit layout. If we are in aarch32
// mode, we need to map these to banked ARM32 registers.
if (inAArch64(tc)) {
- tc->setIntReg(INTREG_X0 + i, value);
+ tc->setReg(int_reg::x(i), value);
} else {
- tc->setIntRegFlat(IntReg64Map[INTREG_X0 + i], value);
+ tc->setRegFlat(int_reg::x(i), value);
}
}
for (const auto &ri : intRegMap) {
const auto value(getOneRegU64(ri.kvm));
DPRINTF(KvmContext, " %s := 0x%x\n", ri.name, value);
- tc->setIntReg(ri.idx, value);
+ tc->setReg(RegId(IntRegClass, ri.idx), value);
}
for (int i = 0; i < NUM_QREGS; ++i) {
diff --git a/src/arch/arm/kvm/armv8_cpu.hh b/src/arch/arm/kvm/armv8_cpu.hh
index adca379..c66d2d2 100644
--- a/src/arch/arm/kvm/armv8_cpu.hh
+++ b/src/arch/arm/kvm/armv8_cpu.hh
@@ -97,13 +97,13 @@
/** Mapping between integer registers in gem5 and KVM */
struct IntRegInfo
{
- IntRegInfo(uint64_t _kvm, ArmISA::IntRegIndex _idx, const char *_name)
+ IntRegInfo(uint64_t _kvm, RegIndex _idx, const char *_name)
: kvm(_kvm), idx(_idx), name(_name) {}
/** Register index in KVM */
uint64_t kvm;
/** Register index in gem5 */
- ArmISA::IntRegIndex idx;
+ RegIndex idx;
/** Name to use in debug dumps */
const char *name;
};
diff --git a/src/arch/arm/linux/fs_workload.cc b/src/arch/arm/linux/fs_workload.cc
index e724eb1..26146ef 100644
--- a/src/arch/arm/linux/fs_workload.cc
+++ b/src/arch/arm/linux/fs_workload.cc
@@ -179,15 +179,15 @@
// originally done because the entry offset changed in kernel v5.8.
// Previously the bootloader just used a hardcoded address.
for (auto *tc: system->threads) {
- tc->setIntReg(0, params().dtb_addr);
- tc->setIntReg(5, params().cpu_release_addr);
+ tc->setReg(int_reg::X0, params().dtb_addr);
+ tc->setReg(int_reg::X5, params().cpu_release_addr);
}
} else {
// Kernel boot requirements to set up r0, r1 and r2 in ARMv7
for (auto *tc: system->threads) {
- tc->setIntReg(0, 0);
- tc->setIntReg(1, params().machine_type);
- tc->setIntReg(2, params().dtb_addr);
+ tc->setReg(int_reg::R0, (RegVal)0);
+ tc->setReg(int_reg::R1, params().machine_type);
+ tc->setReg(int_reg::R2, params().dtb_addr);
}
}
}
@@ -301,7 +301,7 @@
uint32_t &tgid, std::string &next_task_str, int32_t &mm) {
linux::ThreadInfo ti(tc);
- Addr task_descriptor = tc->readIntReg(2);
+ Addr task_descriptor = tc->getReg(int_reg::R2);
pid = ti.curTaskPID(task_descriptor);
tgid = ti.curTaskTGID(task_descriptor);
next_task_str = ti.curTaskName(task_descriptor);
@@ -323,7 +323,7 @@
uint32_t &tgid, std::string &next_task_str, int32_t &mm) {
linux::ThreadInfo ti(tc);
- Addr task_struct = tc->readIntReg(1);
+ Addr task_struct = tc->getReg(int_reg::X1);
pid = ti.curTaskPIDFromTaskStruct(task_struct);
tgid = ti.curTaskTGIDFromTaskStruct(task_struct);
next_task_str = ti.curTaskNameFromTaskStruct(task_struct);
diff --git a/src/arch/arm/linux/linux.hh b/src/arch/arm/linux/linux.hh
index 66c2f9e..6c19981 100644
--- a/src/arch/arm/linux/linux.hh
+++ b/src/arch/arm/linux/linux.hh
@@ -290,7 +290,7 @@
ArmLinux::archClone(flags, pp, cp, ptc, ctc, stack, tls);
if (stack)
- ctc->setIntReg(ArmISA::INTREG_SP, stack);
+ ctc->setReg(ArmISA::int_reg::Sp, stack);
}
};
@@ -544,7 +544,7 @@
ArmLinux::archClone(flags, pp, cp, ptc, ctc, stack, tls);
if (stack)
- ctc->setIntReg(ArmISA::INTREG_SP0, stack);
+ ctc->setReg(ArmISA::int_reg::Sp0, stack);
}
};
diff --git a/src/arch/arm/linux/se_workload.cc b/src/arch/arm/linux/se_workload.cc
index 9cbae93..c919d85 100644
--- a/src/arch/arm/linux/se_workload.cc
+++ b/src/arch/arm/linux/se_workload.cc
@@ -872,14 +872,14 @@
SyscallDesc *desc = nullptr;
if (dynamic_cast<ArmLinuxProcess64 *>(process)) {
- int num = tc->readIntReg(INTREG_X8);
+ int num = tc->getReg(int_reg::X8);
desc = syscallDescs64Low.get(num, false);
if (!desc)
desc = syscallDescs64Low.get(num, false);
if (!desc)
desc = privSyscallDescs64.get(num);
} else {
- int num = tc->readIntReg(INTREG_R7);
+ int num = tc->getReg(int_reg::R7);
desc = syscallDescs32Low.get(num, false);
if (!desc)
desc = syscallDescs32Low.get(num, false);
diff --git a/src/arch/arm/linux/se_workload.hh b/src/arch/arm/linux/se_workload.hh
index f0af647..0939af1 100644
--- a/src/arch/arm/linux/se_workload.hh
+++ b/src/arch/arm/linux/se_workload.hh
@@ -74,9 +74,9 @@
static void
store(ThreadContext *tc, const SyscallReturn &ret)
{
- tc->setIntReg(ArmISA::ReturnValueReg, ret.encodedValue());
+ tc->setReg(ArmISA::ReturnValueReg, ret.encodedValue());
if (ret.count() > 1)
- tc->setIntReg(ArmISA::SyscallPseudoReturnReg, ret.value2());
+ tc->setReg(ArmISA::SyscallPseudoReturnReg, ret.value2());
}
};
diff --git a/src/arch/arm/nativetrace.cc b/src/arch/arm/nativetrace.cc
index ca3f0c4..11bd5d9 100644
--- a/src/arch/arm/nativetrace.cc
+++ b/src/arch/arm/nativetrace.cc
@@ -109,7 +109,7 @@
// Regular int regs
for (int i = 0; i < 15; i++) {
- newState[i] = tc->readIntReg(i);
+ newState[i] = tc->getReg(RegId(IntRegClass, i));
changed[i] = (oldState[i] != newState[i]);
}
diff --git a/src/arch/arm/process.cc b/src/arch/arm/process.cc
index a2b0b60..9770ea6 100644
--- a/src/arch/arm/process.cc
+++ b/src/arch/arm/process.cc
@@ -107,7 +107,7 @@
ArmProcess32::initState()
{
Process::initState();
- argsInit<uint32_t>(PageBytes, INTREG_SP);
+ argsInit<uint32_t>(PageBytes, int_reg::Sp);
for (auto id: contextIds) {
ThreadContext *tc = system->threads[id];
CPACR cpacr = tc->readMiscReg(MISCREG_CPACR);
@@ -126,7 +126,7 @@
ArmProcess64::initState()
{
Process::initState();
- argsInit<uint64_t>(PageBytes, INTREG_SP0);
+ argsInit<uint64_t>(PageBytes, int_reg::Sp0);
for (auto id: contextIds) {
ThreadContext *tc = system->threads[id];
CPSR cpsr = tc->readMiscReg(MISCREG_CPSR);
@@ -257,7 +257,7 @@
template <class IntType>
void
-ArmProcess::argsInit(int pageSize, IntRegIndex spIndex)
+ArmProcess::argsInit(int pageSize, const RegId &spId)
{
int intSize = sizeof(IntType);
@@ -449,22 +449,22 @@
ThreadContext *tc = system->threads[contextIds[0]];
//Set the stack pointer register
- tc->setIntReg(spIndex, memState->getStackMin());
+ tc->setReg(spId, memState->getStackMin());
//A pointer to a function to run when the program exits. We'll set this
//to zero explicitly to make sure this isn't used.
- tc->setIntReg(ArgumentReg0, 0);
+ tc->setReg(ArgumentReg0, (RegVal)0);
//Set argument regs 1 and 2 to argv[0] and envp[0] respectively
if (argv.size() > 0) {
- tc->setIntReg(ArgumentReg1, arg_data_base + arg_data_size -
- argv[argv.size() - 1].size() - 1);
+ tc->setReg(ArgumentReg1, arg_data_base + arg_data_size -
+ argv[argv.size() - 1].size() - 1);
} else {
- tc->setIntReg(ArgumentReg1, 0);
+ tc->setReg(ArgumentReg1, (RegVal)0);
}
if (envp.size() > 0) {
- tc->setIntReg(ArgumentReg2, env_data_base + env_data_size -
- envp[envp.size() - 1].size() - 1);
+ tc->setReg(ArgumentReg2, env_data_base + env_data_size -
+ envp[envp.size() - 1].size() - 1);
} else {
- tc->setIntReg(ArgumentReg2, 0);
+ tc->setReg(ArgumentReg2, (RegVal)0);
}
PCState pc;
diff --git a/src/arch/arm/process.hh b/src/arch/arm/process.hh
index de6d171..6bdabef 100644
--- a/src/arch/arm/process.hh
+++ b/src/arch/arm/process.hh
@@ -60,7 +60,7 @@
ArmProcess(const ProcessParams ¶ms, loader::ObjectFile *objFile,
loader::Arch _arch);
template<class IntType>
- void argsInit(int pageSize, ArmISA::IntRegIndex spIndex);
+ void argsInit(int pageSize, const RegId &spId);
template<class IntType>
IntType
diff --git a/src/arch/arm/regs/int.hh b/src/arch/arm/regs/int.hh
index 3646a36..34c2685 100644
--- a/src/arch/arm/regs/int.hh
+++ b/src/arch/arm/regs/int.hh
@@ -45,6 +45,7 @@
#include "arch/arm/types.hh"
#include "base/logging.hh"
+#include "cpu/reg_class.hh"
#include "sim/core.hh"
namespace gem5
@@ -62,445 +63,516 @@
SignedBitfield<31, 0> sw;
EndBitUnion(PackedIntReg)
-enum IntRegIndex
+namespace int_reg
+{
+
+enum : RegIndex
{
/* All the unique register indices. */
- INTREG_R0,
- INTREG_R1,
- INTREG_R2,
- INTREG_R3,
- INTREG_R4,
- INTREG_R5,
- INTREG_R6,
- INTREG_R7,
- INTREG_R8,
- INTREG_R9,
- INTREG_R10,
- INTREG_R11,
- INTREG_R12,
- INTREG_R13,
- INTREG_SP = INTREG_R13,
- INTREG_R14,
- INTREG_LR = INTREG_R14,
- INTREG_R15,
- INTREG_PC = INTREG_R15,
+ _R0Idx,
+ _R1Idx,
+ _R2Idx,
+ _R3Idx,
+ _R4Idx,
+ _R5Idx,
+ _R6Idx,
+ _R7Idx,
+ _R8Idx,
+ _R9Idx,
+ _R10Idx,
+ _R11Idx,
+ _R12Idx,
+ _R13Idx,
+ _R14Idx,
+ _R15Idx,
- INTREG_R13_SVC,
- INTREG_SP_SVC = INTREG_R13_SVC,
- INTREG_R14_SVC,
- INTREG_LR_SVC = INTREG_R14_SVC,
+ _R13SvcIdx,
+ _R14SvcIdx,
- INTREG_R13_MON,
- INTREG_SP_MON = INTREG_R13_MON,
- INTREG_R14_MON,
- INTREG_LR_MON = INTREG_R14_MON,
+ _R13MonIdx,
+ _R14MonIdx,
- INTREG_R13_HYP,
- INTREG_SP_HYP = INTREG_R13_HYP,
+ _R13HypIdx,
- INTREG_R13_ABT,
- INTREG_SP_ABT = INTREG_R13_ABT,
- INTREG_R14_ABT,
- INTREG_LR_ABT = INTREG_R14_ABT,
+ _R13AbtIdx,
+ _R14AbtIdx,
- INTREG_R13_UND,
- INTREG_SP_UND = INTREG_R13_UND,
- INTREG_R14_UND,
- INTREG_LR_UND = INTREG_R14_UND,
+ _R13UndIdx,
+ _R14UndIdx,
- INTREG_R13_IRQ,
- INTREG_SP_IRQ = INTREG_R13_IRQ,
- INTREG_R14_IRQ,
- INTREG_LR_IRQ = INTREG_R14_IRQ,
+ _R13IrqIdx,
+ _R14IrqIdx,
- INTREG_R8_FIQ,
- INTREG_R9_FIQ,
- INTREG_R10_FIQ,
- INTREG_R11_FIQ,
- INTREG_R12_FIQ,
- INTREG_R13_FIQ,
- INTREG_SP_FIQ = INTREG_R13_FIQ,
- INTREG_R14_FIQ,
- INTREG_LR_FIQ = INTREG_R14_FIQ,
+ _R8FiqIdx,
+ _R9FiqIdx,
+ _R10FiqIdx,
+ _R11FiqIdx,
+ _R12FiqIdx,
+ _R13FiqIdx,
+ _R14FiqIdx,
- INTREG_ZERO,
- INTREG_UREG0,
- INTREG_UREG1,
- INTREG_UREG2,
+ _ZeroIdx,
+ _Ureg0Idx,
+ _Ureg1Idx,
+ _Ureg2Idx,
- INTREG_SP0,
- INTREG_SP1,
- INTREG_SP2,
- INTREG_SP3,
+ _Sp0Idx,
+ _Sp1Idx,
+ _Sp2Idx,
+ _Sp3Idx,
- NUM_INTREGS,
- NUM_ARCH_INTREGS = 32,
+ NumRegs,
+ _SpxIdx = NumRegs,
- /* AArch64 registers */
- INTREG_X0 = 0,
- INTREG_X1,
- INTREG_X2,
- INTREG_X3,
- INTREG_X4,
- INTREG_X5,
- INTREG_X6,
- INTREG_X7,
- INTREG_X8,
- INTREG_X9,
- INTREG_X10,
- INTREG_X11,
- INTREG_X12,
- INTREG_X13,
- INTREG_X14,
- INTREG_X15,
- INTREG_X16,
- INTREG_X17,
- INTREG_X18,
- INTREG_X19,
- INTREG_X20,
- INTREG_X21,
- INTREG_X22,
- INTREG_X23,
- INTREG_X24,
- INTREG_X25,
- INTREG_X26,
- INTREG_X27,
- INTREG_X28,
- INTREG_X29,
- INTREG_X30,
- INTREG_X31,
+ NumArchRegs = 32,
- INTREG_SPX = NUM_INTREGS,
+ _X0Idx = 0,
+ _X1Idx,
+ _X2Idx,
+ _X3Idx,
+ _X4Idx,
+ _X5Idx,
+ _X6Idx,
+ _X7Idx,
+ _X8Idx,
+ _X9Idx,
+ _X10Idx,
+ _X11Idx,
+ _X12Idx,
+ _X13Idx,
+ _X14Idx,
+ _X15Idx,
+ _X16Idx,
+ _X17Idx,
+ _X18Idx,
+ _X19Idx,
+ _X20Idx,
+ _X21Idx,
+ _X22Idx,
+ _X23Idx,
+ _X24Idx,
+ _X25Idx,
+ _X26Idx,
+ _X27Idx,
+ _X28Idx,
+ _X29Idx,
+ _X30Idx,
+ _X31Idx
+};
- /* All the aliased indexes. */
+inline constexpr RegId
+ /* All the unique register indices. */
+ R0(IntRegClass, _R0Idx),
+ R1(IntRegClass, _R1Idx),
+ R2(IntRegClass, _R2Idx),
+ R3(IntRegClass, _R3Idx),
+ R4(IntRegClass, _R4Idx),
+ R5(IntRegClass, _R5Idx),
+ R6(IntRegClass, _R6Idx),
+ R7(IntRegClass, _R7Idx),
+ R8(IntRegClass, _R8Idx),
+ R9(IntRegClass, _R9Idx),
+ R10(IntRegClass, _R10Idx),
+ R11(IntRegClass, _R11Idx),
+ R12(IntRegClass, _R12Idx),
+ R13(IntRegClass, _R13Idx),
+ R14(IntRegClass, _R14Idx),
+ R15(IntRegClass, _R15Idx),
+
+ R13Svc(IntRegClass, _R13SvcIdx),
+ R14Svc(IntRegClass, _R14SvcIdx),
+
+ R13Mon(IntRegClass, _R13MonIdx),
+ R14Mon(IntRegClass, _R14MonIdx),
+
+ R13Hyp(IntRegClass, _R13HypIdx),
+
+ R13Abt(IntRegClass, _R13AbtIdx),
+ R14Abt(IntRegClass, _R14AbtIdx),
+
+ R13Und(IntRegClass, _R13UndIdx),
+ R14Und(IntRegClass, _R14UndIdx),
+
+ R13Irq(IntRegClass, _R13IrqIdx),
+ R14Irq(IntRegClass, _R14IrqIdx),
+
+ R8Fiq(IntRegClass, _R8FiqIdx),
+ R9Fiq(IntRegClass, _R9FiqIdx),
+ R10Fiq(IntRegClass, _R10FiqIdx),
+ R11Fiq(IntRegClass, _R11FiqIdx),
+ R12Fiq(IntRegClass, _R12FiqIdx),
+ R13Fiq(IntRegClass, _R13FiqIdx),
+ R14Fiq(IntRegClass, _R14FiqIdx),
+
+ Zero(IntRegClass, _ZeroIdx),
+ Ureg0(IntRegClass, _Ureg0Idx),
+ Ureg1(IntRegClass, _Ureg1Idx),
+ Ureg2(IntRegClass, _Ureg2Idx),
+
+ Sp0(IntRegClass, _Sp0Idx),
+ Sp1(IntRegClass, _Sp1Idx),
+ Sp2(IntRegClass, _Sp2Idx),
+ Sp3(IntRegClass, _Sp3Idx),
+
+ Spx(IntRegClass, _SpxIdx),
+
+ X0(IntRegClass, _X0Idx),
+ X1(IntRegClass, _X1Idx),
+ X2(IntRegClass, _X2Idx),
+ X3(IntRegClass, _X3Idx),
+ X4(IntRegClass, _X4Idx),
+ X5(IntRegClass, _X5Idx),
+ X6(IntRegClass, _X6Idx),
+ X7(IntRegClass, _X7Idx),
+ X8(IntRegClass, _X8Idx),
+ X9(IntRegClass, _X9Idx),
+ X10(IntRegClass, _X10Idx),
+ X11(IntRegClass, _X11Idx),
+ X12(IntRegClass, _X12Idx),
+ X13(IntRegClass, _X13Idx),
+ X14(IntRegClass, _X14Idx),
+ X15(IntRegClass, _X15Idx),
+ X16(IntRegClass, _X16Idx),
+ X17(IntRegClass, _X17Idx),
+ X18(IntRegClass, _X18Idx),
+ X19(IntRegClass, _X19Idx),
+ X20(IntRegClass, _X20Idx),
+ X21(IntRegClass, _X21Idx),
+ X22(IntRegClass, _X22Idx),
+ X23(IntRegClass, _X23Idx),
+ X24(IntRegClass, _X24Idx),
+ X25(IntRegClass, _X25Idx),
+ X26(IntRegClass, _X26Idx),
+ X27(IntRegClass, _X27Idx),
+ X28(IntRegClass, _X28Idx),
+ X29(IntRegClass, _X29Idx),
+ X30(IntRegClass, _X30Idx),
+ X31(IntRegClass, _X31Idx);
+
+inline constexpr auto
+ &Sp = R13,
+ &Lr = R14,
+ &Pc = R15,
+
+ &SpSvc = R13Svc,
+ &LRSvc = R14Svc,
+
+ &SPMon = R13Mon,
+ &LRMon = R14Mon,
+
+ &SPHyp = R13Hyp,
+
+ &SPAbt = R13Abt,
+ &LRAbt = R14Abt,
+
+ &SPUnd = R13Und,
+ &LRUnd = R14Und,
+
+ &SPIrq = R13Irq,
+ &LRIrq = R14Irq,
+
+ &SPFiq = R13Fiq,
+ &LRFiq = R14Fiq,
/* USR mode */
- INTREG_R0_USR = INTREG_R0,
- INTREG_R1_USR = INTREG_R1,
- INTREG_R2_USR = INTREG_R2,
- INTREG_R3_USR = INTREG_R3,
- INTREG_R4_USR = INTREG_R4,
- INTREG_R5_USR = INTREG_R5,
- INTREG_R6_USR = INTREG_R6,
- INTREG_R7_USR = INTREG_R7,
- INTREG_R8_USR = INTREG_R8,
- INTREG_R9_USR = INTREG_R9,
- INTREG_R10_USR = INTREG_R10,
- INTREG_R11_USR = INTREG_R11,
- INTREG_R12_USR = INTREG_R12,
- INTREG_R13_USR = INTREG_R13,
- INTREG_SP_USR = INTREG_SP,
- INTREG_R14_USR = INTREG_R14,
- INTREG_LR_USR = INTREG_LR,
- INTREG_R15_USR = INTREG_R15,
- INTREG_PC_USR = INTREG_PC,
+ &R0Usr = R0,
+ &R1Usr = R1,
+ &R2Usr = R2,
+ &R3Usr = R3,
+ &R4Usr = R4,
+ &R5Usr = R5,
+ &R6Usr = R6,
+ &R7Usr = R7,
+ &R8Usr = R8,
+ &R9Usr = R9,
+ &R10Usr = R10,
+ &R11Usr = R11,
+ &R12Usr = R12,
+ &R13Usr = R13,
+ &SPUsr = Sp,
+ &R14Usr = R14,
+ &LRUsr = Lr,
+ &R15Usr = R15,
+ &PcUsr = Pc,
/* SVC mode */
- INTREG_R0_SVC = INTREG_R0,
- INTREG_R1_SVC = INTREG_R1,
- INTREG_R2_SVC = INTREG_R2,
- INTREG_R3_SVC = INTREG_R3,
- INTREG_R4_SVC = INTREG_R4,
- INTREG_R5_SVC = INTREG_R5,
- INTREG_R6_SVC = INTREG_R6,
- INTREG_R7_SVC = INTREG_R7,
- INTREG_R8_SVC = INTREG_R8,
- INTREG_R9_SVC = INTREG_R9,
- INTREG_R10_SVC = INTREG_R10,
- INTREG_R11_SVC = INTREG_R11,
- INTREG_R12_SVC = INTREG_R12,
- INTREG_PC_SVC = INTREG_PC,
- INTREG_R15_SVC = INTREG_R15,
+ &R0Svc = R0,
+ &R1Svc = R1,
+ &R2Svc = R2,
+ &R3Svc = R3,
+ &R4Svc = R4,
+ &R5Svc = R5,
+ &R6Svc = R6,
+ &R7Svc = R7,
+ &R8Svc = R8,
+ &R9Svc = R9,
+ &R10Svc = R10,
+ &R11Svc = R11,
+ &R12Svc = R12,
+ &PcSvc = Pc,
+ &R15Svc = R15,
/* MON mode */
- INTREG_R0_MON = INTREG_R0,
- INTREG_R1_MON = INTREG_R1,
- INTREG_R2_MON = INTREG_R2,
- INTREG_R3_MON = INTREG_R3,
- INTREG_R4_MON = INTREG_R4,
- INTREG_R5_MON = INTREG_R5,
- INTREG_R6_MON = INTREG_R6,
- INTREG_R7_MON = INTREG_R7,
- INTREG_R8_MON = INTREG_R8,
- INTREG_R9_MON = INTREG_R9,
- INTREG_R10_MON = INTREG_R10,
- INTREG_R11_MON = INTREG_R11,
- INTREG_R12_MON = INTREG_R12,
- INTREG_PC_MON = INTREG_PC,
- INTREG_R15_MON = INTREG_R15,
+ &R0Mon = R0,
+ &R1Mon = R1,
+ &R2Mon = R2,
+ &R3Mon = R3,
+ &R4Mon = R4,
+ &R5Mon = R5,
+ &R6Mon = R6,
+ &R7Mon = R7,
+ &R8Mon = R8,
+ &R9Mon = R9,
+ &R10Mon = R10,
+ &R11Mon = R11,
+ &R12Mon = R12,
+ &PcMon = Pc,
+ &R15Mon = R15,
/* ABT mode */
- INTREG_R0_ABT = INTREG_R0,
- INTREG_R1_ABT = INTREG_R1,
- INTREG_R2_ABT = INTREG_R2,
- INTREG_R3_ABT = INTREG_R3,
- INTREG_R4_ABT = INTREG_R4,
- INTREG_R5_ABT = INTREG_R5,
- INTREG_R6_ABT = INTREG_R6,
- INTREG_R7_ABT = INTREG_R7,
- INTREG_R8_ABT = INTREG_R8,
- INTREG_R9_ABT = INTREG_R9,
- INTREG_R10_ABT = INTREG_R10,
- INTREG_R11_ABT = INTREG_R11,
- INTREG_R12_ABT = INTREG_R12,
- INTREG_PC_ABT = INTREG_PC,
- INTREG_R15_ABT = INTREG_R15,
+ &R0Abt = R0,
+ &R1Abt = R1,
+ &R2Abt = R2,
+ &R3Abt = R3,
+ &R4Abt = R4,
+ &R5Abt = R5,
+ &R6Abt = R6,
+ &R7Abt = R7,
+ &R8Abt = R8,
+ &R9Abt = R9,
+ &R10Abt = R10,
+ &R11Abt = R11,
+ &R12Abt = R12,
+ &PcAbt = Pc,
+ &R15Abt = R15,
/* HYP mode */
- INTREG_R0_HYP = INTREG_R0,
- INTREG_R1_HYP = INTREG_R1,
- INTREG_R2_HYP = INTREG_R2,
- INTREG_R3_HYP = INTREG_R3,
- INTREG_R4_HYP = INTREG_R4,
- INTREG_R5_HYP = INTREG_R5,
- INTREG_R6_HYP = INTREG_R6,
- INTREG_R7_HYP = INTREG_R7,
- INTREG_R8_HYP = INTREG_R8,
- INTREG_R9_HYP = INTREG_R9,
- INTREG_R10_HYP = INTREG_R10,
- INTREG_R11_HYP = INTREG_R11,
- INTREG_R12_HYP = INTREG_R12,
- INTREG_LR_HYP = INTREG_LR,
- INTREG_R14_HYP = INTREG_R14,
- INTREG_PC_HYP = INTREG_PC,
- INTREG_R15_HYP = INTREG_R15,
+ &R0Hyp = R0,
+ &R1Hyp = R1,
+ &R2Hyp = R2,
+ &R3Hyp = R3,
+ &R4Hyp = R4,
+ &R5Hyp = R5,
+ &R6Hyp = R6,
+ &R7Hyp = R7,
+ &R8Hyp = R8,
+ &R9Hyp = R9,
+ &R10Hyp = R10,
+ &R11Hyp = R11,
+ &R12Hyp = R12,
+ &LRHyp = Lr,
+ &R14Hyp = R14,
+ &PcHyp = Pc,
+ &R15Hyp = R15,
/* UND mode */
- INTREG_R0_UND = INTREG_R0,
- INTREG_R1_UND = INTREG_R1,
- INTREG_R2_UND = INTREG_R2,
- INTREG_R3_UND = INTREG_R3,
- INTREG_R4_UND = INTREG_R4,
- INTREG_R5_UND = INTREG_R5,
- INTREG_R6_UND = INTREG_R6,
- INTREG_R7_UND = INTREG_R7,
- INTREG_R8_UND = INTREG_R8,
- INTREG_R9_UND = INTREG_R9,
- INTREG_R10_UND = INTREG_R10,
- INTREG_R11_UND = INTREG_R11,
- INTREG_R12_UND = INTREG_R12,
- INTREG_PC_UND = INTREG_PC,
- INTREG_R15_UND = INTREG_R15,
+ &R0Und = R0,
+ &R1Und = R1,
+ &R2Und = R2,
+ &R3Und = R3,
+ &R4Und = R4,
+ &R5Und = R5,
+ &R6Und = R6,
+ &R7Und = R7,
+ &R8Und = R8,
+ &R9Und = R9,
+ &R10Und = R10,
+ &R11Und = R11,
+ &R12Und = R12,
+ &PcUnd = Pc,
+ &R15Und = R15,
/* IRQ mode */
- INTREG_R0_IRQ = INTREG_R0,
- INTREG_R1_IRQ = INTREG_R1,
- INTREG_R2_IRQ = INTREG_R2,
- INTREG_R3_IRQ = INTREG_R3,
- INTREG_R4_IRQ = INTREG_R4,
- INTREG_R5_IRQ = INTREG_R5,
- INTREG_R6_IRQ = INTREG_R6,
- INTREG_R7_IRQ = INTREG_R7,
- INTREG_R8_IRQ = INTREG_R8,
- INTREG_R9_IRQ = INTREG_R9,
- INTREG_R10_IRQ = INTREG_R10,
- INTREG_R11_IRQ = INTREG_R11,
- INTREG_R12_IRQ = INTREG_R12,
- INTREG_PC_IRQ = INTREG_PC,
- INTREG_R15_IRQ = INTREG_R15,
+ &R0Irq = R0,
+ &R1Irq = R1,
+ &R2Irq = R2,
+ &R3Irq = R3,
+ &R4Irq = R4,
+ &R5Irq = R5,
+ &R6Irq = R6,
+ &R7Irq = R7,
+ &R8Irq = R8,
+ &R9Irq = R9,
+ &R10Irq = R10,
+ &R11Irq = R11,
+ &R12Irq = R12,
+ &PcIrq = Pc,
+ &R15Irq = R15,
/* FIQ mode */
- INTREG_R0_FIQ = INTREG_R0,
- INTREG_R1_FIQ = INTREG_R1,
- INTREG_R2_FIQ = INTREG_R2,
- INTREG_R3_FIQ = INTREG_R3,
- INTREG_R4_FIQ = INTREG_R4,
- INTREG_R5_FIQ = INTREG_R5,
- INTREG_R6_FIQ = INTREG_R6,
- INTREG_R7_FIQ = INTREG_R7,
- INTREG_PC_FIQ = INTREG_PC,
- INTREG_R15_FIQ = INTREG_R15
+ &R0Fiq = R0,
+ &R1Fiq = R1,
+ &R2Fiq = R2,
+ &R3Fiq = R3,
+ &R4Fiq = R4,
+ &R5Fiq = R5,
+ &R6Fiq = R6,
+ &R7Fiq = R7,
+ &PcFiq = Pc,
+ &R15Fiq = R15;
+
+typedef const RegId RegMap[NumArchRegs];
+
+const RegMap Reg64Map = {
+ R0, R1, R2, R3, R4, R5, R6, R7,
+ R8Usr, R9Usr, R10Usr, R11Usr, R12Usr, R13Usr, R14Usr, R13Hyp,
+ R14Irq, R13Irq, R14Svc, R13Svc, R14Abt, R13Abt, R14Und, R13Und,
+ R8Fiq, R9Fiq, R10Fiq, R11Fiq, R12Fiq, R13Fiq, R14Fiq, Zero
};
-typedef IntRegIndex IntRegMap[NUM_ARCH_INTREGS];
-
-const IntRegMap IntReg64Map = {
- INTREG_R0, INTREG_R1, INTREG_R2, INTREG_R3,
- INTREG_R4, INTREG_R5, INTREG_R6, INTREG_R7,
- INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
- INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R13_HYP,
- INTREG_R14_IRQ, INTREG_R13_IRQ, INTREG_R14_SVC, INTREG_R13_SVC,
- INTREG_R14_ABT, INTREG_R13_ABT, INTREG_R14_UND, INTREG_R13_UND,
- INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
- INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_ZERO
-};
-
-const IntRegMap IntRegUsrMap = {
- INTREG_R0_USR, INTREG_R1_USR, INTREG_R2_USR, INTREG_R3_USR,
- INTREG_R4_USR, INTREG_R5_USR, INTREG_R6_USR, INTREG_R7_USR,
- INTREG_R8_USR, INTREG_R9_USR, INTREG_R10_USR, INTREG_R11_USR,
- INTREG_R12_USR, INTREG_R13_USR, INTREG_R14_USR, INTREG_R15_USR,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
-};
-
-static inline IntRegIndex
-INTREG_USR(unsigned index)
+static inline RegId
+x(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegUsrMap[index];
+ assert(index < NumArchRegs);
+ return RegId(IntRegClass, _X0Idx + index);
}
-const IntRegMap IntRegHypMap = {
- INTREG_R0_HYP, INTREG_R1_HYP, INTREG_R2_HYP, INTREG_R3_HYP,
- INTREG_R4_HYP, INTREG_R5_HYP, INTREG_R6_HYP, INTREG_R7_HYP,
- INTREG_R8_HYP, INTREG_R9_HYP, INTREG_R10_HYP, INTREG_R11_HYP,
- INTREG_R12_HYP, INTREG_R13_HYP, INTREG_R14_HYP, INTREG_R15_HYP,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
+const RegMap RegUsrMap = {
+ R0Usr, R1Usr, R2Usr, R3Usr, R4Usr, R5Usr, R6Usr, R7Usr,
+ R8Usr, R9Usr, R10Usr, R11Usr, R12Usr, R13Usr, R14Usr, R15Usr,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
};
-static inline IntRegIndex
-INTREG_HYP(unsigned index)
+static inline const RegId &
+usr(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegHypMap[index];
+ assert(index < NumArchRegs);
+ return RegUsrMap[index];
}
-const IntRegMap IntRegSvcMap = {
- INTREG_R0_SVC, INTREG_R1_SVC, INTREG_R2_SVC, INTREG_R3_SVC,
- INTREG_R4_SVC, INTREG_R5_SVC, INTREG_R6_SVC, INTREG_R7_SVC,
- INTREG_R8_SVC, INTREG_R9_SVC, INTREG_R10_SVC, INTREG_R11_SVC,
- INTREG_R12_SVC, INTREG_R13_SVC, INTREG_R14_SVC, INTREG_R15_SVC,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
+const RegMap RegHypMap = {
+ R0Hyp, R1Hyp, R2Hyp, R3Hyp, R4Hyp, R5Hyp, R6Hyp, R7Hyp,
+ R8Hyp, R9Hyp, R10Hyp, R11Hyp, R12Hyp, R13Hyp, R14Hyp, R15Hyp,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
};
-static inline IntRegIndex
-INTREG_SVC(unsigned index)
+static inline const RegId &
+hyp(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegSvcMap[index];
+ assert(index < NumArchRegs);
+ return RegHypMap[index];
}
-const IntRegMap IntRegMonMap = {
- INTREG_R0_MON, INTREG_R1_MON, INTREG_R2_MON, INTREG_R3_MON,
- INTREG_R4_MON, INTREG_R5_MON, INTREG_R6_MON, INTREG_R7_MON,
- INTREG_R8_MON, INTREG_R9_MON, INTREG_R10_MON, INTREG_R11_MON,
- INTREG_R12_MON, INTREG_R13_MON, INTREG_R14_MON, INTREG_R15_MON,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
+const RegMap RegSvcMap = {
+ R0Svc, R1Svc, R2Svc, R3Svc, R4Svc, R5Svc, R6Svc, R7Svc,
+ R8Svc, R9Svc, R10Svc, R11Svc, R12Svc, R13Svc, R14Svc, R15Svc,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
};
-static inline IntRegIndex
-INTREG_MON(unsigned index)
+static inline const RegId &
+svc(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegMonMap[index];
+ assert(index < NumArchRegs);
+ return RegSvcMap[index];
}
-const IntRegMap IntRegAbtMap = {
- INTREG_R0_ABT, INTREG_R1_ABT, INTREG_R2_ABT, INTREG_R3_ABT,
- INTREG_R4_ABT, INTREG_R5_ABT, INTREG_R6_ABT, INTREG_R7_ABT,
- INTREG_R8_ABT, INTREG_R9_ABT, INTREG_R10_ABT, INTREG_R11_ABT,
- INTREG_R12_ABT, INTREG_R13_ABT, INTREG_R14_ABT, INTREG_R15_ABT,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
+const RegMap RegMonMap = {
+ R0Mon, R1Mon, R2Mon, R3Mon, R4Mon, R5Mon, R6Mon, R7Mon,
+ R8Mon, R9Mon, R10Mon, R11Mon, R12Mon, R13Mon, R14Mon, R15Mon,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
};
-static inline IntRegIndex
-INTREG_ABT(unsigned index)
+static inline const RegId &
+mon(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegAbtMap[index];
+ assert(index < NumArchRegs);
+ return RegMonMap[index];
}
-const IntRegMap IntRegUndMap = {
- INTREG_R0_UND, INTREG_R1_UND, INTREG_R2_UND, INTREG_R3_UND,
- INTREG_R4_UND, INTREG_R5_UND, INTREG_R6_UND, INTREG_R7_UND,
- INTREG_R8_UND, INTREG_R9_UND, INTREG_R10_UND, INTREG_R11_UND,
- INTREG_R12_UND, INTREG_R13_UND, INTREG_R14_UND, INTREG_R15_UND,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
+const RegMap RegAbtMap = {
+ R0Abt, R1Abt, R2Abt, R3Abt, R4Abt, R5Abt, R6Abt, R7Abt,
+ R8Abt, R9Abt, R10Abt, R11Abt, R12Abt, R13Abt, R14Abt, R15Abt,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
};
-static inline IntRegIndex
-INTREG_UND(unsigned index)
+static inline const RegId &
+abt(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegUndMap[index];
+ assert(index < NumArchRegs);
+ return RegAbtMap[index];
}
-const IntRegMap IntRegIrqMap = {
- INTREG_R0_IRQ, INTREG_R1_IRQ, INTREG_R2_IRQ, INTREG_R3_IRQ,
- INTREG_R4_IRQ, INTREG_R5_IRQ, INTREG_R6_IRQ, INTREG_R7_IRQ,
- INTREG_R8_IRQ, INTREG_R9_IRQ, INTREG_R10_IRQ, INTREG_R11_IRQ,
- INTREG_R12_IRQ, INTREG_R13_IRQ, INTREG_R14_IRQ, INTREG_R15_IRQ,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
+const RegMap RegUndMap = {
+ R0Und, R1Und, R2Und, R3Und, R4Und, R5Und, R6Und, R7Und,
+ R8Und, R9Und, R10Und, R11Und, R12Und, R13Und, R14Und, R15Und,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
};
-static inline IntRegIndex
-INTREG_IRQ(unsigned index)
+static inline const RegId &
+und(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegIrqMap[index];
+ assert(index < NumArchRegs);
+ return RegUndMap[index];
}
-const IntRegMap IntRegFiqMap = {
- INTREG_R0_FIQ, INTREG_R1_FIQ, INTREG_R2_FIQ, INTREG_R3_FIQ,
- INTREG_R4_FIQ, INTREG_R5_FIQ, INTREG_R6_FIQ, INTREG_R7_FIQ,
- INTREG_R8_FIQ, INTREG_R9_FIQ, INTREG_R10_FIQ, INTREG_R11_FIQ,
- INTREG_R12_FIQ, INTREG_R13_FIQ, INTREG_R14_FIQ, INTREG_R15_FIQ,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO,
- INTREG_ZERO, INTREG_ZERO, INTREG_ZERO, INTREG_ZERO
+const RegMap RegIrqMap = {
+ R0Irq, R1Irq, R2Irq, R3Irq, R4Irq, R5Irq, R6Irq, R7Irq,
+ R8Irq, R9Irq, R10Irq, R11Irq, R12Irq, R13Irq, R14Irq, R15Irq,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
};
-static inline IntRegIndex
-INTREG_FIQ(unsigned index)
+static inline const RegId &
+irq(unsigned index)
{
- assert(index < NUM_ARCH_INTREGS);
- return IntRegFiqMap[index];
+ assert(index < NumArchRegs);
+ return RegIrqMap[index];
}
-static const unsigned intRegsPerMode = NUM_INTREGS;
+const RegMap RegFiqMap = {
+ R0Fiq, R1Fiq, R2Fiq, R3Fiq, R4Fiq, R5Fiq, R6Fiq, R7Fiq,
+ R8Fiq, R9Fiq, R10Fiq, R11Fiq, R12Fiq, R13Fiq, R14Fiq, R15Fiq,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero,
+ Zero, Zero, Zero, Zero, Zero, Zero, Zero, Zero
+};
+
+static inline const RegId &
+fiq(unsigned index)
+{
+ assert(index < NumArchRegs);
+ return RegFiqMap[index];
+}
+
+static const unsigned regsPerMode = NumRegs;
static inline int
-intRegInMode(OperatingMode mode, int reg)
+regInMode(OperatingMode mode, int reg)
{
- assert(reg < NUM_ARCH_INTREGS);
- return mode * intRegsPerMode + reg;
+ assert(reg < NumArchRegs);
+ return mode * regsPerMode + reg;
}
+} // namespace int_reg
+
static inline int
flattenIntRegModeIndex(int reg)
{
- int mode = reg / intRegsPerMode;
- reg = reg % intRegsPerMode;
+ int mode = reg / int_reg::regsPerMode;
+ reg = reg % int_reg::regsPerMode;
switch (mode) {
case MODE_USER:
case MODE_SYSTEM:
- return INTREG_USR(reg);
+ return int_reg::usr(reg);
case MODE_FIQ:
- return INTREG_FIQ(reg);
+ return int_reg::fiq(reg);
case MODE_IRQ:
- return INTREG_IRQ(reg);
+ return int_reg::irq(reg);
case MODE_SVC:
- return INTREG_SVC(reg);
+ return int_reg::svc(reg);
case MODE_MON:
- return INTREG_MON(reg);
+ return int_reg::mon(reg);
case MODE_ABORT:
- return INTREG_ABT(reg);
+ return int_reg::abt(reg);
case MODE_HYP:
- return INTREG_HYP(reg);
+ return int_reg::hyp(reg);
case MODE_UNDEFINED:
- return INTREG_UND(reg);
+ return int_reg::und(reg);
default:
panic("%d: Flattening into an unknown mode: reg:%#x mode:%#x\n",
curTick(), reg, mode);
@@ -508,64 +580,62 @@
}
-static inline IntRegIndex
-makeSP(IntRegIndex reg)
+static inline RegIndex
+makeSP(RegIndex reg)
{
- if (reg == INTREG_X31)
- reg = INTREG_SPX;
+ if (reg == int_reg::X31)
+ reg = int_reg::Spx;
return reg;
}
static inline bool
couldBeSP(RegIndex reg)
{
- return (reg == INTREG_X31 || reg == INTREG_SPX);
+ return (reg == int_reg::X31 || reg == int_reg::Spx);
}
static inline bool
isSP(RegIndex reg)
{
- return reg == INTREG_SPX;
+ return reg == int_reg::Spx;
}
static inline bool
couldBeZero(RegIndex reg)
{
- return (reg == INTREG_X31 || reg == INTREG_ZERO);
+ return (reg == int_reg::X31 || reg == int_reg::Zero);
}
static inline bool
isZero(RegIndex reg)
{
- return reg == INTREG_ZERO;
+ return reg == int_reg::Zero;
}
-static inline IntRegIndex
-makeZero(IntRegIndex reg)
+static inline RegIndex
+makeZero(RegIndex reg)
{
- if (reg == INTREG_X31)
- reg = INTREG_ZERO;
+ if (reg == int_reg::X31)
+ reg = int_reg::Zero;
return reg;
}
// Semantically meaningful register indices
-const int ReturnValueReg = 0;
-const int ReturnValueReg1 = 1;
-const int ReturnValueReg2 = 2;
-const int NumArgumentRegs = 4;
-const int NumArgumentRegs64 = 8;
-const int ArgumentReg0 = 0;
-const int ArgumentReg1 = 1;
-const int ArgumentReg2 = 2;
-const int ArgumentReg3 = 3;
-const int FramePointerReg = 11;
-const int StackPointerReg = INTREG_SP;
-const int ReturnAddressReg = INTREG_LR;
-const int PCReg = INTREG_PC;
+inline constexpr size_t NumArgumentRegs = 4;
+inline constexpr size_t NumArgumentRegs64 = 8;
+inline constexpr auto
+ &ReturnValueReg = int_reg::X0,
+ &ReturnValueReg1 = int_reg::X1,
+ &ArgumentReg0 = int_reg::X0,
+ &ArgumentReg1 = int_reg::X1,
+ &ArgumentReg2 = int_reg::X2,
+ &FramePointerReg = int_reg::X11,
+ &StackPointerReg = int_reg::Sp,
+ &ReturnAddressReg = int_reg::Lr,
-const int SyscallNumReg = ReturnValueReg;
-const int SyscallPseudoReturnReg = ReturnValueReg;
-const int SyscallSuccessReg = ReturnValueReg;
+ &SyscallNumReg = ReturnValueReg,
+ &SyscallPseudoReturnReg = ReturnValueReg,
+ &SyscallSuccessReg = ReturnValueReg;
} // namespace ArmISA
} // namespace gem5
diff --git a/src/arch/arm/remote_gdb.cc b/src/arch/arm/remote_gdb.cc
index 6e8923e..2f89e2f 100644
--- a/src/arch/arm/remote_gdb.cc
+++ b/src/arch/arm/remote_gdb.cc
@@ -235,8 +235,8 @@
DPRINTF(GDBAcc, "getRegs in remotegdb \n");
for (int i = 0; i < 31; ++i)
- r.x[i] = context->readIntReg(INTREG_X0 + i);
- r.spx = context->readIntReg(INTREG_SPX);
+ r.x[i] = context->getReg(int_reg::x(i));
+ r.spx = context->getReg(int_reg::Spx);
r.pc = context->pcState().instAddr();
r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
@@ -258,7 +258,7 @@
DPRINTF(GDBAcc, "setRegs in remotegdb \n");
for (int i = 0; i < 31; ++i)
- context->setIntReg(INTREG_X0 + i, r.x[i]);
+ context->setReg(int_reg::x(i), r.x[i]);
auto pc_state = context->pcState().as<PCState>();
pc_state.set(r.pc);
context->pcState(pc_state);
@@ -266,7 +266,7 @@
// Update the stack pointer. This should be done after
// updating CPSR/PSTATE since that might affect how SPX gets
// mapped.
- context->setIntReg(INTREG_SPX, r.spx);
+ context->setReg(int_reg::Spx, r.spx);
size_t base = 0;
for (int i = 0; i < NumVecV8ArchRegs; i++) {
@@ -286,21 +286,21 @@
{
DPRINTF(GDBAcc, "getRegs in remotegdb \n");
- r.gpr[0] = context->readIntReg(INTREG_R0);
- r.gpr[1] = context->readIntReg(INTREG_R1);
- r.gpr[2] = context->readIntReg(INTREG_R2);
- r.gpr[3] = context->readIntReg(INTREG_R3);
- r.gpr[4] = context->readIntReg(INTREG_R4);
- r.gpr[5] = context->readIntReg(INTREG_R5);
- r.gpr[6] = context->readIntReg(INTREG_R6);
- r.gpr[7] = context->readIntReg(INTREG_R7);
- r.gpr[8] = context->readIntReg(INTREG_R8);
- r.gpr[9] = context->readIntReg(INTREG_R9);
- r.gpr[10] = context->readIntReg(INTREG_R10);
- r.gpr[11] = context->readIntReg(INTREG_R11);
- r.gpr[12] = context->readIntReg(INTREG_R12);
- r.gpr[13] = context->readIntReg(INTREG_SP);
- r.gpr[14] = context->readIntReg(INTREG_LR);
+ r.gpr[0] = context->getReg(int_reg::R0);
+ r.gpr[1] = context->getReg(int_reg::R1);
+ r.gpr[2] = context->getReg(int_reg::R2);
+ r.gpr[3] = context->getReg(int_reg::R3);
+ r.gpr[4] = context->getReg(int_reg::R4);
+ r.gpr[5] = context->getReg(int_reg::R5);
+ r.gpr[6] = context->getReg(int_reg::R6);
+ r.gpr[7] = context->getReg(int_reg::R7);
+ r.gpr[8] = context->getReg(int_reg::R8);
+ r.gpr[9] = context->getReg(int_reg::R9);
+ r.gpr[10] = context->getReg(int_reg::R10);
+ r.gpr[11] = context->getReg(int_reg::R11);
+ r.gpr[12] = context->getReg(int_reg::R12);
+ r.gpr[13] = context->getReg(int_reg::Sp);
+ r.gpr[14] = context->getReg(int_reg::Lr);
r.gpr[15] = context->pcState().instAddr();
r.cpsr = context->readMiscRegNoEffect(MISCREG_CPSR);
@@ -316,21 +316,21 @@
{
DPRINTF(GDBAcc, "setRegs in remotegdb \n");
- context->setIntReg(INTREG_R0, r.gpr[0]);
- context->setIntReg(INTREG_R1, r.gpr[1]);
- context->setIntReg(INTREG_R2, r.gpr[2]);
- context->setIntReg(INTREG_R3, r.gpr[3]);
- context->setIntReg(INTREG_R4, r.gpr[4]);
- context->setIntReg(INTREG_R5, r.gpr[5]);
- context->setIntReg(INTREG_R6, r.gpr[6]);
- context->setIntReg(INTREG_R7, r.gpr[7]);
- context->setIntReg(INTREG_R8, r.gpr[8]);
- context->setIntReg(INTREG_R9, r.gpr[9]);
- context->setIntReg(INTREG_R10, r.gpr[10]);
- context->setIntReg(INTREG_R11, r.gpr[11]);
- context->setIntReg(INTREG_R12, r.gpr[12]);
- context->setIntReg(INTREG_SP, r.gpr[13]);
- context->setIntReg(INTREG_LR, r.gpr[14]);
+ context->setReg(int_reg::R0, r.gpr[0]);
+ context->setReg(int_reg::R1, r.gpr[1]);
+ context->setReg(int_reg::R2, r.gpr[2]);
+ context->setReg(int_reg::R3, r.gpr[3]);
+ context->setReg(int_reg::R4, r.gpr[4]);
+ context->setReg(int_reg::R5, r.gpr[5]);
+ context->setReg(int_reg::R6, r.gpr[6]);
+ context->setReg(int_reg::R7, r.gpr[7]);
+ context->setReg(int_reg::R8, r.gpr[8]);
+ context->setReg(int_reg::R9, r.gpr[9]);
+ context->setReg(int_reg::R10, r.gpr[10]);
+ context->setReg(int_reg::R11, r.gpr[11]);
+ context->setReg(int_reg::R12, r.gpr[12]);
+ context->setReg(int_reg::Sp, r.gpr[13]);
+ context->setReg(int_reg::Lr, r.gpr[14]);
PCState pc_state = context->pcState().as<PCState>();
pc_state.set(r.gpr[15]);
context->pcState(pc_state);
diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index ed6fa29..8efe841 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -169,7 +169,7 @@
bool
ArmSemihosting::call64(ThreadContext *tc, bool gem5_ops)
{
- RegVal op = tc->readIntReg(ArmISA::INTREG_X0) & mask(32);
+ RegVal op = tc->getReg(ArmISA::int_reg::X0) & mask(32);
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall<Abi64>(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
@@ -195,7 +195,7 @@
bool
ArmSemihosting::call32(ThreadContext *tc, bool gem5_ops)
{
- RegVal op = tc->readIntReg(ArmISA::INTREG_R0);
+ RegVal op = tc->getReg(ArmISA::int_reg::R0);
if (op > MaxStandardOp && !gem5_ops) {
unrecognizedCall<Abi32>(
tc, "Gem5 semihosting op (0x%x) disabled from here.", op);
diff --git a/src/arch/arm/semihosting.hh b/src/arch/arm/semihosting.hh
index a9bdbad..fe7819c 100644
--- a/src/arch/arm/semihosting.hh
+++ b/src/arch/arm/semihosting.hh
@@ -144,7 +144,7 @@
public:
// For 64 bit semihosting, the params are pointer to by X1.
explicit State(const ThreadContext *tc) :
- StateBase<uint64_t>(tc, tc->readIntReg(ArmISA::INTREG_X1))
+ StateBase<uint64_t>(tc, tc->getReg(ArmISA::int_reg::X1))
{}
};
};
@@ -158,7 +158,7 @@
public:
// For 32 bit semihosting, the params are pointer to by R1.
explicit State(const ThreadContext *tc) :
- StateBase<uint64_t>(tc, tc->readIntReg(ArmISA::INTREG_R1))
+ StateBase<uint64_t>(tc, tc->getReg(ArmISA::int_reg::R1))
{}
};
};
@@ -646,7 +646,7 @@
static void
store(ThreadContext *tc, const ArmSemihosting::RetErrno &err)
{
- tc->setIntReg(ArmISA::INTREG_R0, err.first);
+ tc->setReg(ArmISA::int_reg::R0, err.first);
}
};
@@ -656,7 +656,7 @@
static void
store(ThreadContext *tc, const ArmSemihosting::RetErrno &err)
{
- tc->setIntReg(ArmISA::INTREG_X0, err.first);
+ tc->setReg(ArmISA::int_reg::X0, err.first);
}
};
diff --git a/src/arch/arm/tracers/tarmac_parser.cc b/src/arch/arm/tracers/tarmac_parser.cc
index 7abe1c2..f45df9c 100644
--- a/src/arch/arm/tracers/tarmac_parser.cc
+++ b/src/arch/arm/tracers/tarmac_parser.cc
@@ -755,7 +755,7 @@
switch (it->type) {
case REG_R:
case REG_X:
- values.push_back(thread->readIntReg(it->index));
+ values.push_back(thread->getReg(RegId(IntRegClass, it->index)));
break;
case REG_S:
if (instRecord.isetstate == ISET_A64) {
@@ -1139,25 +1139,25 @@
int base_index = atoi(&buf[1]);
char* pch = strchr(buf, '_');
if (pch == NULL) {
- regRecord.index = INTREG_USR(base_index);
+ regRecord.index = int_reg::usr(base_index);
} else {
++pch;
if (strncmp(pch, "usr", 3) == 0)
- regRecord.index = INTREG_USR(base_index);
+ regRecord.index = int_reg::usr(base_index);
else if (strncmp(pch, "fiq", 3) == 0)
- regRecord.index = INTREG_FIQ(base_index);
+ regRecord.index = int_reg::fiq(base_index);
else if (strncmp(pch, "irq", 3) == 0)
- regRecord.index = INTREG_IRQ(base_index);
+ regRecord.index = int_reg::irq(base_index);
else if (strncmp(pch, "svc", 3) == 0)
- regRecord.index = INTREG_SVC(base_index);
+ regRecord.index = int_reg::svc(base_index);
else if (strncmp(pch, "mon", 3) == 0)
- regRecord.index = INTREG_MON(base_index);
+ regRecord.index = int_reg::mon(base_index);
else if (strncmp(pch, "abt", 3) == 0)
- regRecord.index = INTREG_ABT(base_index);
+ regRecord.index = int_reg::abt(base_index);
else if (strncmp(pch, "und", 3) == 0)
- regRecord.index = INTREG_UND(base_index);
+ regRecord.index = int_reg::und(base_index);
else if (strncmp(pch, "hyp", 3) == 0)
- regRecord.index = INTREG_HYP(base_index);
+ regRecord.index = int_reg::hyp(base_index);
}
} else if (std::tolower(buf[0]) == 'x' && isdigit(buf[1])) {
// X register (A64)
@@ -1186,7 +1186,7 @@
} else if (strncmp(buf, "SP_EL", 5) == 0) {
// A64 stack pointer
regRecord.type = REG_X;
- regRecord.index = INTREG_SP0 + atoi(&buf[5]);
+ regRecord.index = int_reg::Sp0 + atoi(&buf[5]);
} else if (miscRegMap.count(buf)) {
// Misc. register
regRecord.type = REG_MISC;
diff --git a/src/arch/arm/tracers/tarmac_record.cc b/src/arch/arm/tracers/tarmac_record.cc
index 8cd1c81..05bb2e3 100644
--- a/src/arch/arm/tracers/tarmac_record.cc
+++ b/src/arch/arm/tracers/tarmac_record.cc
@@ -270,7 +270,7 @@
regValid = true;
switch (regRelIdx) {
- case PCReg:
+ case int_reg::Pc:
regName = "pc";
break;
case StackPointerReg:
@@ -286,7 +286,7 @@
regName = "r" + std::to_string(regRelIdx);
break;
}
- values[Lo] = thread->readIntReg(regRelIdx);
+ values[Lo] = thread->getReg(RegId(IntRegClass, regRelIdx));
}
void
diff --git a/src/arch/arm/tracers/tarmac_record_v8.cc b/src/arch/arm/tracers/tarmac_record_v8.cc
index f34a183..30e9d1e 100644
--- a/src/arch/arm/tracers/tarmac_record_v8.cc
+++ b/src/arch/arm/tracers/tarmac_record_v8.cc
@@ -97,14 +97,14 @@
{
// Do not trace pseudo register accesses: invalid
// register entry.
- if (regRelIdx > NUM_ARCH_INTREGS) {
+ if (regRelIdx > int_reg::NumArchRegs) {
regValid = false;
return;
}
TraceRegEntry::updateInt(tarmCtx, regRelIdx);
- if ((regRelIdx != PCReg) || (regRelIdx != StackPointerReg) ||
+ if ((regRelIdx != int_reg::Pc) || (regRelIdx != StackPointerReg) ||
(regRelIdx != FramePointerReg) || (regRelIdx != ReturnAddressReg)) {
const auto* arm_inst = static_cast<const ArmStaticInst*>(
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index 34e777c..4339744 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -513,7 +513,7 @@
{
bool is_read;
uint32_t crm;
- IntRegIndex rt;
+ RegIndex rt;
uint32_t crn;
uint32_t opc1;
uint32_t opc2;
@@ -667,7 +667,7 @@
{
bool is_read;
uint32_t crm;
- IntRegIndex rt;
+ RegIndex rt;
uint32_t crn;
uint32_t opc1;
uint32_t opc2;
@@ -732,7 +732,7 @@
uint32_t iss, ExceptionClass *ec)
{
uint32_t crm;
- IntRegIndex rt;
+ RegIndex rt;
uint32_t crn;
uint32_t opc1;
uint32_t opc2;
@@ -1180,18 +1180,18 @@
if (sysM4To3 == 0) {
mode = MODE_USER;
- regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
+ regIdx = int_reg::regInMode(mode, bits(sysM, 2, 0) + 8);
} else if (sysM4To3 == 1) {
mode = MODE_FIQ;
- regIdx = intRegInMode(mode, bits(sysM, 2, 0) + 8);
+ regIdx = int_reg::regInMode(mode, bits(sysM, 2, 0) + 8);
} else if (sysM4To3 == 3) {
if (bits(sysM, 1) == 0) {
mode = MODE_MON;
- regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
+ regIdx = int_reg::regInMode(mode, 14 - bits(sysM, 0));
} else {
mode = MODE_HYP;
if (bits(sysM, 0) == 1) {
- regIdx = intRegInMode(mode, 13); // R13 in HYP
+ regIdx = int_reg::regInMode(mode, 13); // R13 in HYP
} else {
isIntReg = false;
regIdx = MISCREG_ELR_HYP;
@@ -1206,9 +1206,9 @@
((sysM2 && !sysM1) << 2) |
((sysM2 && sysM1) << 3) |
(1 << 4));
- regIdx = intRegInMode(mode, 14 - bits(sysM, 0));
+ regIdx = int_reg::regInMode(mode, 14 - bits(sysM, 0));
// Don't flatten the register here. This is going to go through
- // setIntReg() which will do the flattening
+ // setReg() which will do the flattening
ok &= mode != cpsr.mode;
}
}
diff --git a/src/arch/arm/utility.hh b/src/arch/arm/utility.hh
index 2b377a3..2064fef 100644
--- a/src/arch/arm/utility.hh
+++ b/src/arch/arm/utility.hh
@@ -231,7 +231,7 @@
Affinity getAffinity(ArmSystem *arm_sys, ThreadContext *tc);
static inline uint32_t
-mcrMrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, uint32_t crn,
+mcrMrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, uint32_t crn,
uint32_t opc1, uint32_t opc2)
{
return (isRead << 0) |
@@ -243,19 +243,19 @@
}
static inline void
-mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, IntRegIndex &rt,
+mcrMrcIssExtract(uint32_t iss, bool &isRead, uint32_t &crm, RegIndex &rt,
uint32_t &crn, uint32_t &opc1, uint32_t &opc2)
{
isRead = (iss >> 0) & 0x1;
crm = (iss >> 1) & 0xF;
- rt = (IntRegIndex)((iss >> 5) & 0xF);
+ rt = (RegIndex)((iss >> 5) & 0xF);
crn = (iss >> 10) & 0xF;
opc1 = (iss >> 14) & 0x7;
opc2 = (iss >> 17) & 0x7;
}
static inline uint32_t
-mcrrMrrcIssBuild(bool isRead, uint32_t crm, IntRegIndex rt, IntRegIndex rt2,
+mcrrMrrcIssBuild(bool isRead, uint32_t crm, RegIndex rt, RegIndex rt2,
uint32_t opc1)
{
return (isRead << 0) |
@@ -267,7 +267,7 @@
static inline uint32_t
msrMrs64IssBuild(bool isRead, uint32_t op0, uint32_t op1, uint32_t crn,
- uint32_t crm, uint32_t op2, IntRegIndex rt)
+ uint32_t crm, uint32_t op2, RegIndex rt)
{
return isRead |
(crm << 1) |
@@ -353,7 +353,7 @@
validReg = decodeMrsMsrBankedReg(
sysM, r, isIntReg, regIdx, 0, 0, 0, false);
- return (validReg && isIntReg) ? regIdx : INTREG_ZERO;
+ return (validReg && isIntReg) ? regIdx : int_reg::Zero;
}
/**