# Copyright (c) 2007-2008 The Hewlett-Packard Development Company
# All rights reserved.
#
# The license below extends only to copyright in the software and shall
# not be construed as granting a license to any other intellectual
# property including but not limited to intellectual property relating
# to a hardware implementation of the functionality of the software
# licensed hereunder.  You may use the software subject to the license
# terms below provided that you ensure that this notice is replicated
# unmodified and in its entirety in all distributions of the software,
# modified or unmodified, in source code or in binary form.
#
# Copyright (c) 2008 The Regents of The University of Michigan
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are
# met: redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer;
# redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution;
# neither the name of the copyright holders nor the names of its
# contributors may be used to endorse or promote products derived from
# this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.

microcode = """
    def macroop IN_R_I {
        .adjust_imm trimImm(8)
        limm t1, imm, dataSize=8
        mfence
        ld reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
            nonSpec=True
        mfence
    };

    def macroop IN_VIRT_R_I {
        panic "Virtual mode in isn't implemented!"
    };

    def macroop IN_R_R {
        zexti t2, regm, 15, dataSize=8
        mfence
        ld reg, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
            nonSpec=True
        mfence
    };

    def macroop IN_VIRT_R_R {
        panic "Virtual mode in isn't implemented!"
    };

    def macroop OUT_I_R {
        .adjust_imm trimImm(8)
        limm t1, imm, dataSize=8
        mfence
        st reg, intseg, [1, t1, t0], "IntAddrPrefixIO << 3", addressSize=8, \
            nonSpec=True
        mfence
    };

    def macroop OUT_VIRT_I_R {
        panic "Virtual mode out isn't implemented!"
    };

    def macroop OUT_R_R {
        zexti t2, reg, 15, dataSize=8
        mfence
        st regm, intseg, [1, t2, t0], "IntAddrPrefixIO << 3", addressSize=8, \
            nonSpec=True
        mfence
    };

    def macroop OUT_VIRT_R_R {
        panic "Virtual mode out isn't implemented!"
    };
"""