)]}'
{
  "commit": "60dd3c7d05c41988abfa9833556e2247466f4b26",
  "tree": "2bbbc4523e7523adb544f8e5455499136c1bacb6",
  "parents": [
    "3e1b9dfc0f8ca9bd0e869a6f1bf04dd31f7acb18"
  ],
  "author": {
    "name": "Giacomo Travaglini",
    "email": "giacomo.travaglini@arm.com",
    "time": "Wed Feb 08 10:48:29 2023 +0000"
  },
  "committer": {
    "name": "Giacomo Travaglini",
    "email": "giacomo.travaglini@arm.com",
    "time": "Wed May 17 08:11:06 2023 +0000"
  },
  "message": "arch-arm: Simplify FPSCR writes\n\nThe old logic was setting up a mask which was covering pretty much\nthe entire register, except for the FPSCR[14:13] and FPSCR[6:5]\nregister fields. Those RES0 fields were treated as WI.\nWe simplify this by explicitly marking them as RES0 at construction\ntime\n\nChange-Id: I59942bd98c074349307d27e3a99351ee25f4db95\nSigned-off-by: Giacomo Travaglini \u003cgiacomo.travaglini@arm.com\u003e\nReviewed-by: Richard Cooper \u003crichard.cooper@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/70565\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n",
  "tree_diff": [
    {
      "type": "modify",
      "old_id": "83df61fb404c99d4dd57eb2a0017444eb4e2ecfd",
      "old_mode": 33188,
      "old_path": "src/arch/arm/isa.cc",
      "new_id": "9c8e282e20a0f8d91f5eea6fe5d34c21ec619df4",
      "new_mode": 33188,
      "new_path": "src/arch/arm/isa.cc"
    },
    {
      "type": "modify",
      "old_id": "9203810306c7813edc40fc2b7becdb72c0ba9b01",
      "old_mode": 33188,
      "old_path": "src/arch/arm/regs/misc.cc",
      "new_id": "2d76143e082f22fd6330bc9e5c003e4da39bbe03",
      "new_mode": 33188,
      "new_path": "src/arch/arm/regs/misc.cc"
    }
  ]
}