| commit | 614b608a08ae8b22c844e2874b4fb8aed2732a77 | [log] [tgz] |
|---|---|---|
| author | Yu-hsin Wang <yuhsingw@google.com> | Mon Dec 13 17:54:45 2021 +0800 |
| committer | Yu-hsin Wang <yuhsingw@google.com> | Tue Jan 11 02:11:40 2022 +0000 |
| tree | 1c6a7ffc8d17e0ddad37ae2d1791669beb688889 | |
| parent | e5187e279a0c29762d3a266c59690f603690e328 [diff] |
fastmodel: Add an example reset controller for IrisCpu The example reset controller provides a register interface to config RVBAR and ability to reset the core. Change-Id: I088ddde6f44ff9cc5914afb834ec07a8f7f269fa Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/54065 Reviewed-by: Gabe Black <gabe.black@gmail.com> Maintainer: Gabe Black <gabe.black@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>