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from m5.util import warn

from ...components.processors.cpu_types import CPUTypes
from ...components.boards.x86_board import X86Board
from ...components.memory.single_channel import SingleChannelDDR3_1600
from ...components.processors.simple_processor import SimpleProcessor
from ...components.cachehierarchies.ruby.mesi_two_level_cache_hierarchy \
    import MESITwoLevelCacheHierarchy
from ...coherence_protocol import CoherenceProtocol
from ...isas import ISA
from ...utils.requires import requires


class X86DemoBoard(X86Board):
    """
    This prebuilt X86 board is used for demonstration purposes. It simulates
    an X86 3GHz quad-core system with a 2GB DDR3_1600 memory system. A
    MESI_Two_Level cache hierarchy is set with an l1 data and instruction
    cache, each 32kB with an associativity of 8, and a single bank l2 cache of
    1MB with an associativity of 16.

    **DISCLAIMER**: This board is solely for demonstration purposes. This board
    is not known to be representative of any real-world system or produce
    reliable statistical results.

    Example
    -------

    An example of using the X86DemoBoard can be found in
    `configs/example/gem5_library/x86-ubuntu-run.py`.

    To run:

    ```
    scons build/X86/gem5.opt -j`nproc`
    ./build/X86/gem5.opt configs/example/gem5_library/x86-ubuntu-run.py
    ```

    """

    def __init__(self):
        requires(
            isa_required=ISA.X86,
            coherence_protocol_required=CoherenceProtocol.MESI_TWO_LEVEL,
        )

        warn("The X86DemoBoard is solely for demonstration purposes. "
             "This board is not known to be be representative of any "
             "real-world system. Use with caution.")

        memory = SingleChannelDDR3_1600(size="2GB")
        processor = SimpleProcessor(cpu_type=CPUTypes.TIMING, num_cores=4)
        cache_hierarchy = MESITwoLevelCacheHierarchy(
            l1d_size="32kB",
            l1d_assoc=8,
            l1i_size="32kB",
            l1i_assoc=8,
            l2_size="1MB",
            l2_assoc=16,
            num_l2_banks=1,
        )

        super().__init__(
            clk_freq="3GHz",
            processor=processor,
            memory=memory,
            cache_hierarchy=cache_hierarchy,
        )