mem-cache: Cleanup prefetchers
Prefetcher code had extra variables, dependencies
that could be removed, code duplication, and missing
overrides.
Change-Id: I6e9fbf67a0bdab7eb591893039e088261f52d31a
Signed-off-by: Daniel <odanrc@yahoo.com.br>
Reviewed-on: https://gem5-review.googlesource.com/c/14355
Reviewed-by: Nikos Nikoleris <nikos.nikoleris@arm.com>
Maintainer: Nikos Nikoleris <nikos.nikoleris@arm.com>
diff --git a/src/mem/cache/prefetch/Prefetcher.py b/src/mem/cache/prefetch/Prefetcher.py
index 316a6d0..09717df 100644
--- a/src/mem/cache/prefetch/Prefetcher.py
+++ b/src/mem/cache/prefetch/Prefetcher.py
@@ -65,6 +65,9 @@
]
sys = Param.System(Parent.any, "System this prefetcher belongs to")
+ # Get the block size from the parent (system)
+ block_size = Param.Int(Parent.cache_line_size, "Block size in bytes")
+
on_miss = Param.Bool(False, "Only notify prefetcher on misses")
on_read = Param.Bool(True, "Notify prefetcher on reads")
on_write = Param.Bool(True, "Notify prefetcher on writes")
@@ -109,6 +112,9 @@
cxx_class = 'StridePrefetcher'
cxx_header = "mem/cache/prefetch/stride.hh"
+ # Do not consult stride prefetcher on instruction accesses
+ on_inst = False
+
max_conf = Param.Int(7, "Maximum confidence level")
thresh_conf = Param.Int(4, "Threshold confidence level")
min_conf = Param.Int(0, "Minimum confidence level")
diff --git a/src/mem/cache/prefetch/base.cc b/src/mem/cache/prefetch/base.cc
index 41c02ac..3f5b67e 100644
--- a/src/mem/cache/prefetch/base.cc
+++ b/src/mem/cache/prefetch/base.cc
@@ -63,11 +63,10 @@
}
BasePrefetcher::BasePrefetcher(const BasePrefetcherParams *p)
- : ClockedObject(p), listeners(), cache(nullptr), blkSize(0), lBlkSize(0),
- system(p->sys), onMiss(p->on_miss), onRead(p->on_read),
+ : ClockedObject(p), listeners(), cache(nullptr), blkSize(p->block_size),
+ lBlkSize(floorLog2(blkSize)), onMiss(p->on_miss), onRead(p->on_read),
onWrite(p->on_write), onData(p->on_data), onInst(p->on_inst),
- masterId(system->getMasterId(this)),
- pageBytes(system->getPageBytes()),
+ masterId(p->sys->getMasterId(this)), pageBytes(p->sys->getPageBytes()),
prefetchOnAccess(p->prefetch_on_access)
{
}
@@ -77,6 +76,8 @@
{
assert(!cache);
cache = _cache;
+
+ // If the cache has a different block size from the system's, save it
blkSize = cache->getBlockSize();
lBlkSize = floorLog2(blkSize);
}
@@ -121,19 +122,13 @@
bool
BasePrefetcher::inCache(Addr addr, bool is_secure) const
{
- if (cache->inCache(addr, is_secure)) {
- return true;
- }
- return false;
+ return cache->inCache(addr, is_secure);
}
bool
BasePrefetcher::inMissQueue(Addr addr, bool is_secure) const
{
- if (cache->inMissQueue(addr, is_secure)) {
- return true;
- }
- return false;
+ return cache->inMissQueue(addr, is_secure);
}
bool
diff --git a/src/mem/cache/prefetch/base.hh b/src/mem/cache/prefetch/base.hh
index 394c85c..813d1b9 100644
--- a/src/mem/cache/prefetch/base.hh
+++ b/src/mem/cache/prefetch/base.hh
@@ -60,7 +60,6 @@
class BaseCache;
struct BasePrefetcherParams;
-class System;
class BasePrefetcher : public ClockedObject
{
@@ -90,26 +89,23 @@
/** log_2(block size of the parent cache). */
unsigned lBlkSize;
- /** System we belong to */
- System* system;
-
/** Only consult prefetcher on cache misses? */
- bool onMiss;
+ const bool onMiss;
/** Consult prefetcher on reads? */
- bool onRead;
+ const bool onRead;
/** Consult prefetcher on reads? */
- bool onWrite;
+ const bool onWrite;
/** Consult prefetcher on data accesses? */
- bool onData;
+ const bool onData;
/** Consult prefetcher on instruction accesses? */
- bool onInst;
+ const bool onInst;
/** Request id for prefetches */
- MasterID masterId;
+ const MasterID masterId;
const Addr pageBytes;
@@ -147,7 +143,7 @@
virtual ~BasePrefetcher() {}
- virtual void setCache(BaseCache *_cache);
+ void setCache(BaseCache *_cache);
/**
* Notify prefetcher of cache access (may be any access or just
@@ -159,7 +155,10 @@
virtual Tick nextPrefetchReadyTime() const = 0;
- virtual void regStats();
+ /**
+ * Register local statistics.
+ */
+ void regStats() override;
/**
* Register probe points for this object.
diff --git a/src/mem/cache/prefetch/queued.cc b/src/mem/cache/prefetch/queued.cc
index f9a036d..ce14b5a 100644
--- a/src/mem/cache/prefetch/queued.cc
+++ b/src/mem/cache/prefetch/queued.cc
@@ -91,9 +91,8 @@
// Queue up generated prefetches
for (AddrPriority& pf_info : addresses) {
-
// Block align prefetch address
- pf_info.first &= ~(Addr)(blkSize - 1);
+ pf_info.first = blockAddress(pf_info.first);
pfIdentified++;
DPRINTF(HWPrefetch, "Found a pf candidate addr: %#x, "
@@ -131,7 +130,7 @@
return pkt;
}
-std::list<QueuedPrefetcher::DeferredPacket>::const_iterator
+QueuedPrefetcher::const_iterator
QueuedPrefetcher::inPrefetch(Addr address, bool is_secure) const
{
for (const_iterator dp = pfq.begin(); dp != pfq.end(); dp++) {
diff --git a/src/mem/cache/prefetch/queued.hh b/src/mem/cache/prefetch/queued.hh
index 811818f..774e6ed 100644
--- a/src/mem/cache/prefetch/queued.hh
+++ b/src/mem/cache/prefetch/queued.hh
@@ -98,11 +98,9 @@
const bool tagPrefetch;
using const_iterator = std::list<DeferredPacket>::const_iterator;
- std::list<DeferredPacket>::const_iterator inPrefetch(Addr address,
- bool is_secure) const;
+ const_iterator inPrefetch(Addr address, bool is_secure) const;
using iterator = std::list<DeferredPacket>::iterator;
- std::list<DeferredPacket>::iterator inPrefetch(Addr address,
- bool is_secure);
+ iterator inPrefetch(Addr address, bool is_secure);
// STATS
Stats::Scalar pfIdentified;
@@ -116,19 +114,19 @@
virtual ~QueuedPrefetcher();
void notify(const PacketPtr &pkt) override;
+
PacketPtr insert(AddrPriority& info, bool is_secure);
- // Note: This should really be pure virtual, but doesnt go well with params
virtual void calculatePrefetch(const PacketPtr &pkt,
std::vector<AddrPriority> &addresses) = 0;
- PacketPtr getPacket();
+ PacketPtr getPacket() override;
- Tick nextPrefetchReadyTime() const
+ Tick nextPrefetchReadyTime() const override
{
return pfq.empty() ? MaxTick : pfq.front().tick;
}
- void regStats();
+ void regStats() override;
};
#endif //__MEM_CACHE_PREFETCH_QUEUED_HH__
diff --git a/src/mem/cache/prefetch/stride.cc b/src/mem/cache/prefetch/stride.cc
index efe982a..3cea78e 100644
--- a/src/mem/cache/prefetch/stride.cc
+++ b/src/mem/cache/prefetch/stride.cc
@@ -69,9 +69,6 @@
degree(p->degree),
pcTable(pcTableAssoc, pcTableSets, name())
{
- // Don't consult stride prefetcher on instruction accesses
- onInst = false;
-
assert(isPowerOf2(pcTableSets));
}
diff --git a/src/mem/cache/prefetch/stride.hh b/src/mem/cache/prefetch/stride.hh
index 55cdbc8..03ceec5 100644
--- a/src/mem/cache/prefetch/stride.hh
+++ b/src/mem/cache/prefetch/stride.hh
@@ -119,7 +119,7 @@
StridePrefetcher(const StridePrefetcherParams *p);
void calculatePrefetch(const PacketPtr &pkt,
- std::vector<AddrPriority> &addresses);
+ std::vector<AddrPriority> &addresses) override;
};
#endif // __MEM_CACHE_PREFETCH_STRIDE_HH__
diff --git a/src/mem/cache/prefetch/tagged.cc b/src/mem/cache/prefetch/tagged.cc
index abe6b9d..7561633 100644
--- a/src/mem/cache/prefetch/tagged.cc
+++ b/src/mem/cache/prefetch/tagged.cc
@@ -47,7 +47,7 @@
TaggedPrefetcher::calculatePrefetch(const PacketPtr &pkt,
std::vector<AddrPriority> &addresses)
{
- Addr blkAddr = pkt->getAddr() & ~(Addr)(blkSize-1);
+ Addr blkAddr = pkt->getBlockAddr(blkSize);
for (int d = 1; d <= degree; d++) {
Addr newAddr = blkAddr + d*(blkSize);
diff --git a/src/mem/cache/prefetch/tagged.hh b/src/mem/cache/prefetch/tagged.hh
index 95162aa..8dd8b77 100644
--- a/src/mem/cache/prefetch/tagged.hh
+++ b/src/mem/cache/prefetch/tagged.hh
@@ -44,7 +44,7 @@
class TaggedPrefetcher : public QueuedPrefetcher
{
protected:
- int degree;
+ const int degree;
public:
TaggedPrefetcher(const TaggedPrefetcherParams *p);
@@ -52,7 +52,7 @@
~TaggedPrefetcher() {}
void calculatePrefetch(const PacketPtr &pkt,
- std::vector<AddrPriority> &addresses);
+ std::vector<AddrPriority> &addresses) override;
};
#endif // __MEM_CACHE_PREFETCH_TAGGED_HH__
