| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.525648 # Number of seconds simulated |
| sim_ticks 525647850500 # Number of ticks simulated |
| final_tick 525647850500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| sim_freq 1000000000000 # Frequency of simulated ticks |
| host_inst_rate 304424 # Simulator instruction rate (inst/s) |
| host_op_rate 374786 # Simulator op (including micro ops) rate (op/s) |
| host_tick_rate 249775392 # Simulator tick rate (ticks/s) |
| host_mem_usage 281156 # Number of bytes of host memory used |
| host_seconds 2104.48 # Real time elapsed on the host |
| sim_insts 640655085 # Number of instructions simulated |
| sim_ops 788730744 # Number of ops (including micro ops) simulated |
| system.voltage_domain.voltage 1 # Voltage in Volts |
| system.clk_domain.clock 1000 # Clock period in ticks |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.physmem.bytes_read::cpu.inst 164544 # Number of bytes read from this memory |
| system.physmem.bytes_read::cpu.data 18474496 # Number of bytes read from this memory |
| system.physmem.bytes_read::total 18639040 # Number of bytes read from this memory |
| system.physmem.bytes_inst_read::cpu.inst 164544 # Number of instructions bytes read from this memory |
| system.physmem.bytes_inst_read::total 164544 # Number of instructions bytes read from this memory |
| system.physmem.bytes_written::writebacks 4230272 # Number of bytes written to this memory |
| system.physmem.bytes_written::total 4230272 # Number of bytes written to this memory |
| system.physmem.num_reads::cpu.inst 2571 # Number of read requests responded to by this memory |
| system.physmem.num_reads::cpu.data 288664 # Number of read requests responded to by this memory |
| system.physmem.num_reads::total 291235 # Number of read requests responded to by this memory |
| system.physmem.num_writes::writebacks 66098 # Number of write requests responded to by this memory |
| system.physmem.num_writes::total 66098 # Number of write requests responded to by this memory |
| system.physmem.bw_read::cpu.inst 313031 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::cpu.data 35146146 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_read::total 35459177 # Total read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::cpu.inst 313031 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_inst_read::total 313031 # Instruction read bandwidth from this memory (bytes/s) |
| system.physmem.bw_write::writebacks 8047730 # Write bandwidth from this memory (bytes/s) |
| system.physmem.bw_write::total 8047730 # Write bandwidth from this memory (bytes/s) |
| system.physmem.bw_total::writebacks 8047730 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.inst 313031 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::cpu.data 35146146 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.bw_total::total 43506907 # Total bandwidth to/from this memory (bytes/s) |
| system.physmem.readReqs 291235 # Number of read requests accepted |
| system.physmem.writeReqs 66098 # Number of write requests accepted |
| system.physmem.readBursts 291235 # Number of DRAM read bursts, including those serviced by the write queue |
| system.physmem.writeBursts 66098 # Number of DRAM write bursts, including those merged in the write queue |
| system.physmem.bytesReadDRAM 18619136 # Total number of bytes read from DRAM |
| system.physmem.bytesReadWrQ 19904 # Total number of bytes read from write queue |
| system.physmem.bytesWritten 4228224 # Total number of bytes written to DRAM |
| system.physmem.bytesReadSys 18639040 # Total read bytes from the system interface side |
| system.physmem.bytesWrittenSys 4230272 # Total written bytes from the system interface side |
| system.physmem.servicedByWrQ 311 # Number of DRAM read bursts serviced by the write queue |
| system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one |
| system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| system.physmem.perBankRdBursts::0 18288 # Per bank write bursts |
| system.physmem.perBankRdBursts::1 18134 # Per bank write bursts |
| system.physmem.perBankRdBursts::2 18217 # Per bank write bursts |
| system.physmem.perBankRdBursts::3 18185 # Per bank write bursts |
| system.physmem.perBankRdBursts::4 18292 # Per bank write bursts |
| system.physmem.perBankRdBursts::5 18424 # Per bank write bursts |
| system.physmem.perBankRdBursts::6 18179 # Per bank write bursts |
| system.physmem.perBankRdBursts::7 17990 # Per bank write bursts |
| system.physmem.perBankRdBursts::8 18031 # Per bank write bursts |
| system.physmem.perBankRdBursts::9 18051 # Per bank write bursts |
| system.physmem.perBankRdBursts::10 18108 # Per bank write bursts |
| system.physmem.perBankRdBursts::11 18204 # Per bank write bursts |
| system.physmem.perBankRdBursts::12 18211 # Per bank write bursts |
| system.physmem.perBankRdBursts::13 18269 # Per bank write bursts |
| system.physmem.perBankRdBursts::14 18079 # Per bank write bursts |
| system.physmem.perBankRdBursts::15 18262 # Per bank write bursts |
| system.physmem.perBankWrBursts::0 4171 # Per bank write bursts |
| system.physmem.perBankWrBursts::1 4099 # Per bank write bursts |
| system.physmem.perBankWrBursts::2 4134 # Per bank write bursts |
| system.physmem.perBankWrBursts::3 4146 # Per bank write bursts |
| system.physmem.perBankWrBursts::4 4223 # Per bank write bursts |
| system.physmem.perBankWrBursts::5 4224 # Per bank write bursts |
| system.physmem.perBankWrBursts::6 4173 # Per bank write bursts |
| system.physmem.perBankWrBursts::7 4094 # Per bank write bursts |
| system.physmem.perBankWrBursts::8 4093 # Per bank write bursts |
| system.physmem.perBankWrBursts::9 4093 # Per bank write bursts |
| system.physmem.perBankWrBursts::10 4096 # Per bank write bursts |
| system.physmem.perBankWrBursts::11 4097 # Per bank write bursts |
| system.physmem.perBankWrBursts::12 4095 # Per bank write bursts |
| system.physmem.perBankWrBursts::13 4095 # Per bank write bursts |
| system.physmem.perBankWrBursts::14 4095 # Per bank write bursts |
| system.physmem.perBankWrBursts::15 4138 # Per bank write bursts |
| system.physmem.numRdRetry 0 # Number of times read queue was full causing retry |
| system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| system.physmem.totGap 525647749500 # Total gap between requests |
| system.physmem.readPktSize::0 0 # Read request sizes (log2) |
| system.physmem.readPktSize::1 0 # Read request sizes (log2) |
| system.physmem.readPktSize::2 0 # Read request sizes (log2) |
| system.physmem.readPktSize::3 0 # Read request sizes (log2) |
| system.physmem.readPktSize::4 0 # Read request sizes (log2) |
| system.physmem.readPktSize::5 0 # Read request sizes (log2) |
| system.physmem.readPktSize::6 291235 # Read request sizes (log2) |
| system.physmem.writePktSize::0 0 # Write request sizes (log2) |
| system.physmem.writePktSize::1 0 # Write request sizes (log2) |
| system.physmem.writePktSize::2 0 # Write request sizes (log2) |
| system.physmem.writePktSize::3 0 # Write request sizes (log2) |
| system.physmem.writePktSize::4 0 # Write request sizes (log2) |
| system.physmem.writePktSize::5 0 # Write request sizes (log2) |
| system.physmem.writePktSize::6 66098 # Write request sizes (log2) |
| system.physmem.rdQLenPdf::0 290544 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::1 368 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::2 12 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::3 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::4 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see |
| system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
| system.physmem.wrQLenPdf::0 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::1 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::2 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::3 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::4 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::5 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::6 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::7 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::8 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::9 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::10 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::11 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::12 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::13 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::15 890 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::16 890 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::17 4008 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::18 4018 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::19 4019 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::20 4019 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::21 4019 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::22 4019 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::23 4019 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::24 4019 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::25 4020 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::26 4020 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::27 4021 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::28 4021 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::29 4020 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::30 4023 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::31 4020 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::32 4018 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see |
| system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| system.physmem.bytesPerActivate::samples 102644 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::mean 222.570282 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::gmean 147.559533 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::stdev 262.016403 # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::0-127 36015 35.09% 35.09% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::128-255 41909 40.83% 75.92% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::256-383 13148 12.81% 88.73% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::384-511 1006 0.98% 89.71% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::512-639 491 0.48% 90.18% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::640-767 1034 1.01% 91.19% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::768-895 399 0.39% 91.58% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::896-1023 481 0.47% 92.05% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::1024-1151 8161 7.95% 100.00% # Bytes accessed per row activation |
| system.physmem.bytesPerActivate::total 102644 # Bytes accessed per row activation |
| system.physmem.rdPerTurnAround::samples 4018 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::mean 48.515182 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::gmean 34.167653 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::stdev 506.604541 # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::0-1023 4016 99.95% 99.95% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::2048-3071 1 0.02% 99.98% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::31744-32767 1 0.02% 100.00% # Reads before turning the bus around for writes |
| system.physmem.rdPerTurnAround::total 4018 # Reads before turning the bus around for writes |
| system.physmem.wrPerTurnAround::samples 4018 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::mean 16.442509 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::gmean 16.422441 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::stdev 0.830286 # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::16 3129 77.87% 77.87% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::18 889 22.13% 100.00% # Writes before turning the bus around for reads |
| system.physmem.wrPerTurnAround::total 4018 # Writes before turning the bus around for reads |
| system.physmem.totQLat 15528676000 # Total ticks spent queuing |
| system.physmem.totMemAccLat 20983501000 # Total ticks spent from burst creation until serviced by the DRAM |
| system.physmem.totBusLat 1454620000 # Total ticks spent in databus transfers |
| system.physmem.avgQLat 53377.09 # Average queueing delay per DRAM burst |
| system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| system.physmem.avgMemAccLat 72127.09 # Average memory access latency per DRAM burst |
| system.physmem.avgRdBW 35.42 # Average DRAM read bandwidth in MiByte/s |
| system.physmem.avgWrBW 8.04 # Average achieved write bandwidth in MiByte/s |
| system.physmem.avgRdBWSys 35.46 # Average system read bandwidth in MiByte/s |
| system.physmem.avgWrBWSys 8.05 # Average system write bandwidth in MiByte/s |
| system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| system.physmem.busUtil 0.34 # Data bus utilization in percentage |
| system.physmem.busUtilRead 0.28 # Data bus utilization in percentage for reads |
| system.physmem.busUtilWrite 0.06 # Data bus utilization in percentage for writes |
| system.physmem.avgRdQLen 1.00 # Average read queue length when enqueuing |
| system.physmem.avgWrQLen 28.92 # Average write queue length when enqueuing |
| system.physmem.readRowHits 202546 # Number of row buffer hits during reads |
| system.physmem.writeRowHits 51789 # Number of row buffer hits during writes |
| system.physmem.readRowHitRate 69.62 # Row buffer hit rate for reads |
| system.physmem.writeRowHitRate 78.35 # Row buffer hit rate for writes |
| system.physmem.avgGap 1471030.52 # Average gap between requests |
| system.physmem.pageHitRate 71.24 # Row buffer hit rate, read and write combined |
| system.physmem_0.actEnergy 366410520 # Energy for activate commands per rank (pJ) |
| system.physmem_0.preEnergy 194736630 # Energy for precharge commands per rank (pJ) |
| system.physmem_0.readEnergy 1040362260 # Energy for read commands per rank (pJ) |
| system.physmem_0.writeEnergy 173638080 # Energy for write commands per rank (pJ) |
| system.physmem_0.refreshEnergy 28886236080.000008 # Energy for refresh commands per rank (pJ) |
| system.physmem_0.actBackEnergy 8300918550 # Energy for active background per rank (pJ) |
| system.physmem_0.preBackEnergy 1634993280 # Energy for precharge background per rank (pJ) |
| system.physmem_0.actPowerDownEnergy 57345491820 # Energy for active power-down per rank (pJ) |
| system.physmem_0.prePowerDownEnergy 51305938080 # Energy for precharge power-down per rank (pJ) |
| system.physmem_0.selfRefreshEnergy 64928910000 # Energy for self refresh per rank (pJ) |
| system.physmem_0.totalEnergy 214198815120 # Total energy per rank (pJ) |
| system.physmem_0.averagePower 407.494892 # Core power per rank (mW) |
| system.physmem_0.totalIdleTime 503139346250 # Total Idle time Per DRAM Rank |
| system.physmem_0.memoryStateTime::IDLE 3209706000 # Time in different power states |
| system.physmem_0.memoryStateTime::REF 12289528000 # Time in different power states |
| system.physmem_0.memoryStateTime::SREF 243772297750 # Time in different power states |
| system.physmem_0.memoryStateTime::PRE_PDN 133609273250 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT 7009209500 # Time in different power states |
| system.physmem_0.memoryStateTime::ACT_PDN 125757836000 # Time in different power states |
| system.physmem_1.actEnergy 366546180 # Energy for activate commands per rank (pJ) |
| system.physmem_1.preEnergy 194797350 # Energy for precharge commands per rank (pJ) |
| system.physmem_1.readEnergy 1036835100 # Energy for read commands per rank (pJ) |
| system.physmem_1.writeEnergy 171226440 # Energy for write commands per rank (pJ) |
| system.physmem_1.refreshEnergy 28725815040.000008 # Energy for refresh commands per rank (pJ) |
| system.physmem_1.actBackEnergy 8187694890 # Energy for active background per rank (pJ) |
| system.physmem_1.preBackEnergy 1628706720 # Energy for precharge background per rank (pJ) |
| system.physmem_1.actPowerDownEnergy 56919000150 # Energy for active power-down per rank (pJ) |
| system.physmem_1.prePowerDownEnergy 51113801760 # Energy for precharge power-down per rank (pJ) |
| system.physmem_1.selfRefreshEnergy 65311053315 # Energy for self refresh per rank (pJ) |
| system.physmem_1.totalEnergy 213675530385 # Total energy per rank (pJ) |
| system.physmem_1.averagePower 406.499389 # Core power per rank (mW) |
| system.physmem_1.totalIdleTime 503405920500 # Total Idle time Per DRAM Rank |
| system.physmem_1.memoryStateTime::IDLE 3197022000 # Time in different power states |
| system.physmem_1.memoryStateTime::REF 12221338000 # Time in different power states |
| system.physmem_1.memoryStateTime::SREF 245475081750 # Time in different power states |
| system.physmem_1.memoryStateTime::PRE_PDN 133108808000 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT 6823284750 # Time in different power states |
| system.physmem_1.memoryStateTime::ACT_PDN 124822316000 # Time in different power states |
| system.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.branchPred.lookups 147257105 # Number of BP lookups |
| system.cpu.branchPred.condPredicted 98226689 # Number of conditional branches predicted |
| system.cpu.branchPred.condIncorrect 1384794 # Number of conditional branches incorrect |
| system.cpu.branchPred.BTBLookups 89640439 # Number of BTB lookups |
| system.cpu.branchPred.BTBHits 63297158 # Number of BTB hits |
| system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| system.cpu.branchPred.BTBHitPct 70.612280 # BTB Hit Percentage |
| system.cpu.branchPred.usedRAS 19276056 # Number of times the RAS was used to get a target. |
| system.cpu.branchPred.RASInCorrect 1321 # Number of incorrect RAS predictions. |
| system.cpu.branchPred.indirectLookups 15995188 # Number of indirect predictor lookups. |
| system.cpu.branchPred.indirectHits 15989428 # Number of indirect target hits. |
| system.cpu.branchPred.indirectMisses 5760 # Number of indirect misses. |
| system.cpu.branchPredindirectMispredicted 1280093 # Number of mispredicted indirect branches. |
| system.cpu_clk_domain.clock 500 # Clock period in ticks |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.dtb.walker.walks 0 # Table walker walks requested |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.dtb.inst_hits 0 # ITB inst hits |
| system.cpu.dtb.inst_misses 0 # ITB inst misses |
| system.cpu.dtb.read_hits 0 # DTB read hits |
| system.cpu.dtb.read_misses 0 # DTB read misses |
| system.cpu.dtb.write_hits 0 # DTB write hits |
| system.cpu.dtb.write_misses 0 # DTB write misses |
| system.cpu.dtb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.dtb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.dtb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.dtb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.dtb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.dtb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.dtb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.dtb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.dtb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.dtb.read_accesses 0 # DTB read accesses |
| system.cpu.dtb.write_accesses 0 # DTB write accesses |
| system.cpu.dtb.inst_accesses 0 # ITB inst accesses |
| system.cpu.dtb.hits 0 # DTB hits |
| system.cpu.dtb.misses 0 # DTB misses |
| system.cpu.dtb.accesses 0 # DTB accesses |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 # Table walker walks requested |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 # ITB inst hits |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 # ITB inst misses |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 # DTB read hits |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 # DTB read misses |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 # DTB write hits |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 # DTB write misses |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 # DTB read accesses |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 # DTB write accesses |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 # ITB inst accesses |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 # DTB hits |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 # DTB misses |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 # DTB accesses |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.itb.walker.walks 0 # Table walker walks requested |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.walker.walkRequestOrigin::total 0 # Table walker requests started/completed, data/inst |
| system.cpu.itb.inst_hits 0 # ITB inst hits |
| system.cpu.itb.inst_misses 0 # ITB inst misses |
| system.cpu.itb.read_hits 0 # DTB read hits |
| system.cpu.itb.read_misses 0 # DTB read misses |
| system.cpu.itb.write_hits 0 # DTB write hits |
| system.cpu.itb.write_misses 0 # DTB write misses |
| system.cpu.itb.flush_tlb 0 # Number of times complete TLB was flushed |
| system.cpu.itb.flush_tlb_mva 0 # Number of times TLB was flushed by MVA |
| system.cpu.itb.flush_tlb_mva_asid 0 # Number of times TLB was flushed by MVA & ASID |
| system.cpu.itb.flush_tlb_asid 0 # Number of times TLB was flushed by ASID |
| system.cpu.itb.flush_entries 0 # Number of entries that have been flushed from TLB |
| system.cpu.itb.align_faults 0 # Number of TLB faults due to alignment restrictions |
| system.cpu.itb.prefetch_faults 0 # Number of TLB faults due to prefetch |
| system.cpu.itb.domain_faults 0 # Number of TLB faults due to domain restrictions |
| system.cpu.itb.perms_faults 0 # Number of TLB faults due to permissions restrictions |
| system.cpu.itb.read_accesses 0 # DTB read accesses |
| system.cpu.itb.write_accesses 0 # DTB write accesses |
| system.cpu.itb.inst_accesses 0 # ITB inst accesses |
| system.cpu.itb.hits 0 # DTB hits |
| system.cpu.itb.misses 0 # DTB misses |
| system.cpu.itb.accesses 0 # DTB accesses |
| system.cpu.workload.numSyscalls 673 # Number of system calls |
| system.cpu.pwrStateResidencyTicks::ON 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.numCycles 1051295701 # number of cpu cycles simulated |
| system.cpu.numWorkItemsStarted 0 # number of work items this cpu started |
| system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| system.cpu.committedInsts 640655085 # Number of instructions committed |
| system.cpu.committedOps 788730744 # Number of ops (including micro ops) committed |
| system.cpu.discardedOps 8620171 # Number of ops (including micro ops) which were discarded before commit |
| system.cpu.numFetchSuspends 0 # Number of times Execute suspended instruction fetching |
| system.cpu.cpi 1.640970 # CPI: cycles per instruction |
| system.cpu.ipc 0.609396 # IPC: instructions per cycle |
| system.cpu.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction |
| system.cpu.op_class_0::IntAlu 385757467 48.91% 48.91% # Class of committed instruction |
| system.cpu.op_class_0::IntMult 5173441 0.66% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::IntDiv 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatAdd 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatCmp 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatCvt 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatMult 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatMultAcc 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatDiv 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatMisc 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::FloatSqrt 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdAdd 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdAddAcc 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdAlu 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdCmp 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdCvt 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdMisc 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdMult 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdMultAcc 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdShift 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdShiftAcc 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdSqrt 0 0.00% 49.56% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAdd 637528 0.08% 49.65% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatAlu 0 0.00% 49.65% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCmp 3187668 0.40% 50.05% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatCvt 2550131 0.32% 50.37% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatDiv 0 0.00% 50.37% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMisc 10203074 1.29% 51.67% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMult 0 0.00% 51.67% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatMultAcc 0 0.00% 51.67% # Class of committed instruction |
| system.cpu.op_class_0::SimdFloatSqrt 0 0.00% 51.67% # Class of committed instruction |
| system.cpu.op_class_0::MemRead 245222568 31.09% 82.76% # Class of committed instruction |
| system.cpu.op_class_0::MemWrite 125149823 15.87% 98.62% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemRead 7018370 0.89% 99.51% # Class of committed instruction |
| system.cpu.op_class_0::FloatMemWrite 3830674 0.49% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction |
| system.cpu.op_class_0::total 788730744 # Class of committed instruction |
| system.cpu.tickCycles 955914808 # Number of cycles that the object actually ticked |
| system.cpu.idleCycles 95380893 # Total number of cycles that the object has spent stopped |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.tags.replacements 778100 # number of replacements |
| system.cpu.dcache.tags.tagsinuse 4092.107040 # Cycle average of tags in use |
| system.cpu.dcache.tags.total_refs 378447440 # Total number of references to valid blocks. |
| system.cpu.dcache.tags.sampled_refs 782196 # Sample count of references to valid blocks. |
| system.cpu.dcache.tags.avg_refs 483.826867 # Average number of references to valid blocks. |
| system.cpu.dcache.tags.warmup_cycle 850680500 # Cycle when the warmup percentage was hit. |
| system.cpu.dcache.tags.occ_blocks::cpu.data 4092.107040 # Average occupied blocks per requestor |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.999050 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_percent::total 0.999050 # Average percentage of cache occupancy |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 30 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 969 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::3 1388 # Occupied blocks per task id |
| system.cpu.dcache.tags.age_task_id_blocks_1024::4 1537 # Occupied blocks per task id |
| system.cpu.dcache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| system.cpu.dcache.tags.tag_accesses 759379166 # Number of tag accesses |
| system.cpu.dcache.tags.data_accesses 759379166 # Number of data accesses |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.dcache.ReadReq_hits::cpu.data 249618713 # number of ReadReq hits |
| system.cpu.dcache.ReadReq_hits::total 249618713 # number of ReadReq hits |
| system.cpu.dcache.WriteReq_hits::cpu.data 128813765 # number of WriteReq hits |
| system.cpu.dcache.WriteReq_hits::total 128813765 # number of WriteReq hits |
| system.cpu.dcache.SoftPFReq_hits::cpu.data 3484 # number of SoftPFReq hits |
| system.cpu.dcache.SoftPFReq_hits::total 3484 # number of SoftPFReq hits |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 5739 # number of LoadLockedReq hits |
| system.cpu.dcache.LoadLockedReq_hits::total 5739 # number of LoadLockedReq hits |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 5739 # number of StoreCondReq hits |
| system.cpu.dcache.StoreCondReq_hits::total 5739 # number of StoreCondReq hits |
| system.cpu.dcache.demand_hits::cpu.data 378432478 # number of demand (read+write) hits |
| system.cpu.dcache.demand_hits::total 378432478 # number of demand (read+write) hits |
| system.cpu.dcache.overall_hits::cpu.data 378435962 # number of overall hits |
| system.cpu.dcache.overall_hits::total 378435962 # number of overall hits |
| system.cpu.dcache.ReadReq_misses::cpu.data 713192 # number of ReadReq misses |
| system.cpu.dcache.ReadReq_misses::total 713192 # number of ReadReq misses |
| system.cpu.dcache.WriteReq_misses::cpu.data 137712 # number of WriteReq misses |
| system.cpu.dcache.WriteReq_misses::total 137712 # number of WriteReq misses |
| system.cpu.dcache.SoftPFReq_misses::cpu.data 141 # number of SoftPFReq misses |
| system.cpu.dcache.SoftPFReq_misses::total 141 # number of SoftPFReq misses |
| system.cpu.dcache.demand_misses::cpu.data 850904 # number of demand (read+write) misses |
| system.cpu.dcache.demand_misses::total 850904 # number of demand (read+write) misses |
| system.cpu.dcache.overall_misses::cpu.data 851045 # number of overall misses |
| system.cpu.dcache.overall_misses::total 851045 # number of overall misses |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 37264745000 # number of ReadReq miss cycles |
| system.cpu.dcache.ReadReq_miss_latency::total 37264745000 # number of ReadReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 10940214000 # number of WriteReq miss cycles |
| system.cpu.dcache.WriteReq_miss_latency::total 10940214000 # number of WriteReq miss cycles |
| system.cpu.dcache.demand_miss_latency::cpu.data 48204959000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.demand_miss_latency::total 48204959000 # number of demand (read+write) miss cycles |
| system.cpu.dcache.overall_miss_latency::cpu.data 48204959000 # number of overall miss cycles |
| system.cpu.dcache.overall_miss_latency::total 48204959000 # number of overall miss cycles |
| system.cpu.dcache.ReadReq_accesses::cpu.data 250331905 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.ReadReq_accesses::total 250331905 # number of ReadReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::cpu.data 128951477 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.WriteReq_accesses::total 128951477 # number of WriteReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::cpu.data 3625 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.SoftPFReq_accesses::total 3625 # number of SoftPFReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 5739 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.LoadLockedReq_accesses::total 5739 # number of LoadLockedReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 5739 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.StoreCondReq_accesses::total 5739 # number of StoreCondReq accesses(hits+misses) |
| system.cpu.dcache.demand_accesses::cpu.data 379283382 # number of demand (read+write) accesses |
| system.cpu.dcache.demand_accesses::total 379283382 # number of demand (read+write) accesses |
| system.cpu.dcache.overall_accesses::cpu.data 379287007 # number of overall (read+write) accesses |
| system.cpu.dcache.overall_accesses::total 379287007 # number of overall (read+write) accesses |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.002849 # miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_miss_rate::total 0.002849 # miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.001068 # miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_miss_rate::total 0.001068 # miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.038897 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_miss_rate::total 0.038897 # miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.002243 # miss rate for demand accesses |
| system.cpu.dcache.demand_miss_rate::total 0.002243 # miss rate for demand accesses |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.002244 # miss rate for overall accesses |
| system.cpu.dcache.overall_miss_rate::total 0.002244 # miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 52250.649194 # average ReadReq miss latency |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 52250.649194 # average ReadReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 79442.706518 # average WriteReq miss latency |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 79442.706518 # average WriteReq miss latency |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 56651.465970 # average overall miss latency |
| system.cpu.dcache.demand_avg_miss_latency::total 56651.465970 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 56642.080031 # average overall miss latency |
| system.cpu.dcache.overall_avg_miss_latency::total 56642.080031 # average overall miss latency |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.dcache.writebacks::writebacks 88684 # number of writebacks |
| system.cpu.dcache.writebacks::total 88684 # number of writebacks |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 457 # number of ReadReq MSHR hits |
| system.cpu.dcache.ReadReq_mshr_hits::total 457 # number of ReadReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::cpu.data 68390 # number of WriteReq MSHR hits |
| system.cpu.dcache.WriteReq_mshr_hits::total 68390 # number of WriteReq MSHR hits |
| system.cpu.dcache.demand_mshr_hits::cpu.data 68847 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.demand_mshr_hits::total 68847 # number of demand (read+write) MSHR hits |
| system.cpu.dcache.overall_mshr_hits::cpu.data 68847 # number of overall MSHR hits |
| system.cpu.dcache.overall_mshr_hits::total 68847 # number of overall MSHR hits |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 712735 # number of ReadReq MSHR misses |
| system.cpu.dcache.ReadReq_mshr_misses::total 712735 # number of ReadReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 69322 # number of WriteReq MSHR misses |
| system.cpu.dcache.WriteReq_mshr_misses::total 69322 # number of WriteReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 139 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.SoftPFReq_mshr_misses::total 139 # number of SoftPFReq MSHR misses |
| system.cpu.dcache.demand_mshr_misses::cpu.data 782057 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.demand_mshr_misses::total 782057 # number of demand (read+write) MSHR misses |
| system.cpu.dcache.overall_mshr_misses::cpu.data 782196 # number of overall MSHR misses |
| system.cpu.dcache.overall_mshr_misses::total 782196 # number of overall MSHR misses |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 36543095500 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 36543095500 # number of ReadReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 5486426000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 5486426000 # number of WriteReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 1802000 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 1802000 # number of SoftPFReq MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 42029521500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.demand_mshr_miss_latency::total 42029521500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 42031323500 # number of overall MSHR miss cycles |
| system.cpu.dcache.overall_mshr_miss_latency::total 42031323500 # number of overall MSHR miss cycles |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.002847 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.002847 # mshr miss rate for ReadReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.000538 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.000538 # mshr miss rate for WriteReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.038345 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.038345 # mshr miss rate for SoftPFReq accesses |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for demand accesses |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.002062 # mshr miss rate for demand accesses |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.002062 # mshr miss rate for overall accesses |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.002062 # mshr miss rate for overall accesses |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 51271.644440 # average ReadReq mshr miss latency |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 51271.644440 # average ReadReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 79144.081244 # average WriteReq mshr miss latency |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 79144.081244 # average WriteReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 12964.028777 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 12964.028777 # average SoftPFReq mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53742.273901 # average overall mshr miss latency |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 53742.273901 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53735.027410 # average overall mshr miss latency |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 53735.027410 # average overall mshr miss latency |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.tags.replacements 24889 # number of replacements |
| system.cpu.icache.tags.tagsinuse 1710.890314 # Cycle average of tags in use |
| system.cpu.icache.tags.total_refs 257795451 # Total number of references to valid blocks. |
| system.cpu.icache.tags.sampled_refs 26639 # Sample count of references to valid blocks. |
| system.cpu.icache.tags.avg_refs 9677.369684 # Average number of references to valid blocks. |
| system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| system.cpu.icache.tags.occ_blocks::cpu.inst 1710.890314 # Average occupied blocks per requestor |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.835396 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_percent::total 0.835396 # Average percentage of cache occupancy |
| system.cpu.icache.tags.occ_task_id_blocks::1024 1750 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 56 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::1 96 # Occupied blocks per task id |
| system.cpu.icache.tags.age_task_id_blocks_1024::4 1598 # Occupied blocks per task id |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.854492 # Percentage of cache occupancy per task id |
| system.cpu.icache.tags.tag_accesses 515670821 # Number of tag accesses |
| system.cpu.icache.tags.data_accesses 515670821 # Number of data accesses |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.icache.ReadReq_hits::cpu.inst 257795451 # number of ReadReq hits |
| system.cpu.icache.ReadReq_hits::total 257795451 # number of ReadReq hits |
| system.cpu.icache.demand_hits::cpu.inst 257795451 # number of demand (read+write) hits |
| system.cpu.icache.demand_hits::total 257795451 # number of demand (read+write) hits |
| system.cpu.icache.overall_hits::cpu.inst 257795451 # number of overall hits |
| system.cpu.icache.overall_hits::total 257795451 # number of overall hits |
| system.cpu.icache.ReadReq_misses::cpu.inst 26640 # number of ReadReq misses |
| system.cpu.icache.ReadReq_misses::total 26640 # number of ReadReq misses |
| system.cpu.icache.demand_misses::cpu.inst 26640 # number of demand (read+write) misses |
| system.cpu.icache.demand_misses::total 26640 # number of demand (read+write) misses |
| system.cpu.icache.overall_misses::cpu.inst 26640 # number of overall misses |
| system.cpu.icache.overall_misses::total 26640 # number of overall misses |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 538801500 # number of ReadReq miss cycles |
| system.cpu.icache.ReadReq_miss_latency::total 538801500 # number of ReadReq miss cycles |
| system.cpu.icache.demand_miss_latency::cpu.inst 538801500 # number of demand (read+write) miss cycles |
| system.cpu.icache.demand_miss_latency::total 538801500 # number of demand (read+write) miss cycles |
| system.cpu.icache.overall_miss_latency::cpu.inst 538801500 # number of overall miss cycles |
| system.cpu.icache.overall_miss_latency::total 538801500 # number of overall miss cycles |
| system.cpu.icache.ReadReq_accesses::cpu.inst 257822091 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.ReadReq_accesses::total 257822091 # number of ReadReq accesses(hits+misses) |
| system.cpu.icache.demand_accesses::cpu.inst 257822091 # number of demand (read+write) accesses |
| system.cpu.icache.demand_accesses::total 257822091 # number of demand (read+write) accesses |
| system.cpu.icache.overall_accesses::cpu.inst 257822091 # number of overall (read+write) accesses |
| system.cpu.icache.overall_accesses::total 257822091 # number of overall (read+write) accesses |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000103 # miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_miss_rate::total 0.000103 # miss rate for ReadReq accesses |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.000103 # miss rate for demand accesses |
| system.cpu.icache.demand_miss_rate::total 0.000103 # miss rate for demand accesses |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.000103 # miss rate for overall accesses |
| system.cpu.icache.overall_miss_rate::total 0.000103 # miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 20225.281532 # average ReadReq miss latency |
| system.cpu.icache.ReadReq_avg_miss_latency::total 20225.281532 # average ReadReq miss latency |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency |
| system.cpu.icache.demand_avg_miss_latency::total 20225.281532 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 20225.281532 # average overall miss latency |
| system.cpu.icache.overall_avg_miss_latency::total 20225.281532 # average overall miss latency |
| system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.icache.writebacks::writebacks 24889 # number of writebacks |
| system.cpu.icache.writebacks::total 24889 # number of writebacks |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 26640 # number of ReadReq MSHR misses |
| system.cpu.icache.ReadReq_mshr_misses::total 26640 # number of ReadReq MSHR misses |
| system.cpu.icache.demand_mshr_misses::cpu.inst 26640 # number of demand (read+write) MSHR misses |
| system.cpu.icache.demand_mshr_misses::total 26640 # number of demand (read+write) MSHR misses |
| system.cpu.icache.overall_mshr_misses::cpu.inst 26640 # number of overall MSHR misses |
| system.cpu.icache.overall_mshr_misses::total 26640 # number of overall MSHR misses |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 512162500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 512162500 # number of ReadReq MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 512162500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.demand_mshr_miss_latency::total 512162500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 512162500 # number of overall MSHR miss cycles |
| system.cpu.icache.overall_mshr_miss_latency::total 512162500 # number of overall MSHR miss cycles |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000103 # mshr miss rate for ReadReq accesses |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for demand accesses |
| system.cpu.icache.demand_mshr_miss_rate::total 0.000103 # mshr miss rate for demand accesses |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000103 # mshr miss rate for overall accesses |
| system.cpu.icache.overall_mshr_miss_rate::total 0.000103 # mshr miss rate for overall accesses |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 19225.319069 # average ReadReq mshr miss latency |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 19225.319069 # average ReadReq mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 19225.319069 # average overall mshr miss latency |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 19225.319069 # average overall mshr miss latency |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.tags.replacements 258839 # number of replacements |
| system.cpu.l2cache.tags.tagsinuse 32651.545544 # Cycle average of tags in use |
| system.cpu.l2cache.tags.total_refs 1316953 # Total number of references to valid blocks. |
| system.cpu.l2cache.tags.sampled_refs 291607 # Sample count of references to valid blocks. |
| system.cpu.l2cache.tags.avg_refs 4.516191 # Average number of references to valid blocks. |
| system.cpu.l2cache.tags.warmup_cycle 3958663000 # Cycle when the warmup percentage was hit. |
| system.cpu.l2cache.tags.occ_blocks::writebacks 40.523746 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 90.271478 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 32520.750321 # Average occupied blocks per requestor |
| system.cpu.l2cache.tags.occ_percent::writebacks 0.001237 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.002755 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.992455 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_percent::total 0.996446 # Average percentage of cache occupancy |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 32768 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 122 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 207 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 300 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::3 2912 # Occupied blocks per task id |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::4 29227 # Occupied blocks per task id |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 1 # Percentage of cache occupancy per task id |
| system.cpu.l2cache.tags.tag_accesses 13160335 # Number of tag accesses |
| system.cpu.l2cache.tags.data_accesses 13160335 # Number of data accesses |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.l2cache.WritebackDirty_hits::writebacks 88684 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackDirty_hits::total 88684 # number of WritebackDirty hits |
| system.cpu.l2cache.WritebackClean_hits::writebacks 23557 # number of WritebackClean hits |
| system.cpu.l2cache.WritebackClean_hits::total 23557 # number of WritebackClean hits |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 3231 # number of ReadExReq hits |
| system.cpu.l2cache.ReadExReq_hits::total 3231 # number of ReadExReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 24064 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadCleanReq_hits::total 24064 # number of ReadCleanReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::cpu.data 490275 # number of ReadSharedReq hits |
| system.cpu.l2cache.ReadSharedReq_hits::total 490275 # number of ReadSharedReq hits |
| system.cpu.l2cache.demand_hits::cpu.inst 24064 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::cpu.data 493506 # number of demand (read+write) hits |
| system.cpu.l2cache.demand_hits::total 517570 # number of demand (read+write) hits |
| system.cpu.l2cache.overall_hits::cpu.inst 24064 # number of overall hits |
| system.cpu.l2cache.overall_hits::cpu.data 493506 # number of overall hits |
| system.cpu.l2cache.overall_hits::total 517570 # number of overall hits |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 66091 # number of ReadExReq misses |
| system.cpu.l2cache.ReadExReq_misses::total 66091 # number of ReadExReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 2576 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadCleanReq_misses::total 2576 # number of ReadCleanReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 222599 # number of ReadSharedReq misses |
| system.cpu.l2cache.ReadSharedReq_misses::total 222599 # number of ReadSharedReq misses |
| system.cpu.l2cache.demand_misses::cpu.inst 2576 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::cpu.data 288690 # number of demand (read+write) misses |
| system.cpu.l2cache.demand_misses::total 291266 # number of demand (read+write) misses |
| system.cpu.l2cache.overall_misses::cpu.inst 2576 # number of overall misses |
| system.cpu.l2cache.overall_misses::cpu.data 288690 # number of overall misses |
| system.cpu.l2cache.overall_misses::total 291266 # number of overall misses |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 5348515000 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadExReq_miss_latency::total 5348515000 # number of ReadExReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 218253000 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 218253000 # number of ReadCleanReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 30325726000 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 30325726000 # number of ReadSharedReq miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 218253000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::cpu.data 35674241000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.demand_miss_latency::total 35892494000 # number of demand (read+write) miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 218253000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::cpu.data 35674241000 # number of overall miss cycles |
| system.cpu.l2cache.overall_miss_latency::total 35892494000 # number of overall miss cycles |
| system.cpu.l2cache.WritebackDirty_accesses::writebacks 88684 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackDirty_accesses::total 88684 # number of WritebackDirty accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 23557 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.WritebackClean_accesses::total 23557 # number of WritebackClean accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 69322 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadExReq_accesses::total 69322 # number of ReadExReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 26640 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadCleanReq_accesses::total 26640 # number of ReadCleanReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 712874 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.ReadSharedReq_accesses::total 712874 # number of ReadSharedReq accesses(hits+misses) |
| system.cpu.l2cache.demand_accesses::cpu.inst 26640 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::cpu.data 782196 # number of demand (read+write) accesses |
| system.cpu.l2cache.demand_accesses::total 808836 # number of demand (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.inst 26640 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::cpu.data 782196 # number of overall (read+write) accesses |
| system.cpu.l2cache.overall_accesses::total 808836 # number of overall (read+write) accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.953391 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.953391 # miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.096697 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.096697 # miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.312256 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.312256 # miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.096697 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.369076 # miss rate for demand accesses |
| system.cpu.l2cache.demand_miss_rate::total 0.360105 # miss rate for demand accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.096697 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.369076 # miss rate for overall accesses |
| system.cpu.l2cache.overall_miss_rate::total 0.360105 # miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80926.525548 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80926.525548 # average ReadExReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 84725.543478 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 84725.543478 # average ReadCleanReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 136234.780929 # average ReadSharedReq miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 136234.780929 # average ReadSharedReq miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency |
| system.cpu.l2cache.demand_avg_miss_latency::total 123229.261225 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 84725.543478 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 123572.832450 # average overall miss latency |
| system.cpu.l2cache.overall_avg_miss_latency::total 123229.261225 # average overall miss latency |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked |
| system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| system.cpu.l2cache.writebacks::writebacks 66098 # number of writebacks |
| system.cpu.l2cache.writebacks::total 66098 # number of writebacks |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::cpu.inst 4 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadCleanReq_mshr_hits::total 4 # number of ReadCleanReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::cpu.data 26 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.ReadSharedReq_mshr_hits::total 26 # number of ReadSharedReq MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.inst 4 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::cpu.data 26 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.demand_mshr_hits::total 30 # number of demand (read+write) MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.inst 4 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::cpu.data 26 # number of overall MSHR hits |
| system.cpu.l2cache.overall_mshr_hits::total 30 # number of overall MSHR hits |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 66091 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 66091 # number of ReadExReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 2572 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 2572 # number of ReadCleanReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 222573 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 222573 # number of ReadSharedReq MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 2572 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 288664 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.demand_mshr_misses::total 291236 # number of demand (read+write) MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 2572 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 288664 # number of overall MSHR misses |
| system.cpu.l2cache.overall_mshr_misses::total 291236 # number of overall MSHR misses |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4687605000 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4687605000 # number of ReadExReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 192261000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 192261000 # number of ReadCleanReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 28098015500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 28098015500 # number of ReadSharedReq MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 192261000 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 32785620500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.demand_mshr_miss_latency::total 32977881500 # number of demand (read+write) MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 192261000 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 32785620500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.overall_mshr_miss_latency::total 32977881500 # number of overall MSHR miss cycles |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.953391 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.953391 # mshr miss rate for ReadExReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.096547 # mshr miss rate for ReadCleanReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.312219 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.312219 # mshr miss rate for ReadSharedReq accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for demand accesses |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.360068 # mshr miss rate for demand accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.096547 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.369043 # mshr miss rate for overall accesses |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.360068 # mshr miss rate for overall accesses |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70926.525548 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70926.525548 # average ReadExReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 74751.555210 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 74751.555210 # average ReadCleanReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 126241.797073 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 126241.797073 # average ReadSharedReq mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 74751.555210 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 113577.101752 # average overall mshr miss latency |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 113234.220701 # average overall mshr miss latency |
| system.cpu.toL2Bus.snoop_filter.tot_requests 1611825 # Total number of requests made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 803048 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 3234 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 2033 # Total number of snoops made to the snoop filter. |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 2018 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 15 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.cpu.toL2Bus.trans_dist::ReadResp 739513 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackDirty 154782 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::WritebackClean 24889 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::CleanEvict 882157 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExReq 69322 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadExResp 69322 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 26640 # Transaction distribution |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 712874 # Transaction distribution |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 78168 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2342492 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_count::total 2420660 # Packet count per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 3297792 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 55736320 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.pkt_size::total 59034112 # Cumulative packet size per connected master and slave (bytes) |
| system.cpu.toL2Bus.snoops 258839 # Total snoops (count) |
| system.cpu.toL2Bus.snoopTraffic 4230272 # Total snoop traffic (bytes) |
| system.cpu.toL2Bus.snoop_fanout::samples 1067675 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::mean 0.005002 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.070750 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::0 1062349 99.50% 99.50% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::1 5311 0.50% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::2 15 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::max_value 2 # Request fanout histogram |
| system.cpu.toL2Bus.snoop_fanout::total 1067675 # Request fanout histogram |
| system.cpu.toL2Bus.reqLayer0.occupancy 919485500 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer0.occupancy 39960496 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer0.utilization 0.0 # Layer utilization (%) |
| system.cpu.toL2Bus.respLayer1.occupancy 1173306974 # Layer occupancy (ticks) |
| system.cpu.toL2Bus.respLayer1.utilization 0.2 # Layer utilization (%) |
| system.membus.snoop_filter.tot_requests 548040 # Total number of requests made to the snoop filter. |
| system.membus.snoop_filter.hit_single_requests 256844 # Number of requests hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. |
| system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. |
| system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| system.membus.pwrStateResidencyTicks::UNDEFINED 525647850500 # Cumulative time (in ticks) in various power states |
| system.membus.trans_dist::ReadResp 225144 # Transaction distribution |
| system.membus.trans_dist::WritebackDirty 66098 # Transaction distribution |
| system.membus.trans_dist::CleanEvict 190707 # Transaction distribution |
| system.membus.trans_dist::ReadExReq 66091 # Transaction distribution |
| system.membus.trans_dist::ReadExResp 66091 # Transaction distribution |
| system.membus.trans_dist::ReadSharedReq 225144 # Transaction distribution |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 839275 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_count::total 839275 # Packet count per connected master and slave (bytes) |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 22869312 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.pkt_size::total 22869312 # Cumulative packet size per connected master and slave (bytes) |
| system.membus.snoops 0 # Total snoops (count) |
| system.membus.snoopTraffic 0 # Total snoop traffic (bytes) |
| system.membus.snoop_fanout::samples 291235 # Request fanout histogram |
| system.membus.snoop_fanout::mean 0 # Request fanout histogram |
| system.membus.snoop_fanout::stdev 0 # Request fanout histogram |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| system.membus.snoop_fanout::0 291235 100.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| system.membus.snoop_fanout::min_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::max_value 0 # Request fanout histogram |
| system.membus.snoop_fanout::total 291235 # Request fanout histogram |
| system.membus.reqLayer0.occupancy 917214500 # Layer occupancy (ticks) |
| system.membus.reqLayer0.utilization 0.2 # Layer utilization (%) |
| system.membus.respLayer1.occupancy 1553534250 # Layer occupancy (ticks) |
| system.membus.respLayer1.utilization 0.3 # Layer utilization (%) |
| |
| ---------- End Simulation Statistics ---------- |
