commit 6b6ac525f7bcb4259ef2065919bc9985c48ef35d
author Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Sep 05 10:52:47 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Thu Sep 19 10:54:14 2019 +0000
tree 86987681ecbd6ddb2eb3813f8c610f362eeecad1
parent ee00675d24761f2df22fa588cba8dee7d1050f3a

arch-arm: PSTATE.PAN changes should inval cached regs in TLB

Change-Id: Id94e355fec345d2e952539a7dce7fbd21ed220c6
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20983
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa.cc

diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index b957105..6e65102 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -791,6 +791,10 @@
             getDTBPtr(tc)->invalidateMiscReg();
         }
 
+        if (cpsr.pan != old_cpsr.pan) {
+            getDTBPtr(tc)->invalidateMiscReg();
+        }
+
         DPRINTF(Arm, "Updating CPSR from %#x to %#x f:%d i:%d a:%d mode:%#x\n",
                 miscRegs[misc_reg], cpsr, cpsr.f, cpsr.i, cpsr.a, cpsr.mode);
         PCState pc = tc->pcState();