src/sim/ClockDomain.py

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from m5.params import *
from m5.SimObject import SimObject
from m5.proxy import *

# Abstract clock domain
class ClockDomain(SimObject):
    type = 'ClockDomain'
    cxx_header = "sim/clock_domain.hh"
    cxx_class = 'gem5::ClockDomain'
    abstract = True

# Source clock domain with an actual clock, and a list of voltage and frequency
# op points
class SrcClockDomain(ClockDomain):
    type = 'SrcClockDomain'
    cxx_header = "sim/clock_domain.hh"
    cxx_class = 'gem5::SrcClockDomain'

    # Single clock frequency value, or list of frequencies for DVFS
    # Frequencies must be ordered in descending order
    # Note: Matching voltages should be defined in the voltage domain
    clock = VectorParam.Clock("Clock period")

    # A source clock must be associated with a voltage domain
    voltage_domain = Param.VoltageDomain("Voltage domain")

    # Domain ID is an identifier for the DVFS domain as understood by the
    # necessary control logic (either software or hardware). For example, in
    # case of software control via cpufreq framework the IDs should correspond
    # to the neccessary identifier in the device tree blob which is interpretted
    # by the device driver to communicate to the domain controller in hardware.
    domain_id = Param.Int32(-1, "domain id")

    # Initial performance level from the list of available operation points
    # Defaults to maximum performance
    init_perf_level = Param.UInt32(0, "Initial performance level")

# Derived clock domain with a parent clock domain and a frequency
# divider
class DerivedClockDomain(ClockDomain):
    type = 'DerivedClockDomain'
    cxx_header = "sim/clock_domain.hh"
    cxx_class = 'gem5::DerivedClockDomain'

    clk_domain = Param.ClockDomain("Parent clock domain")
    clk_divider = Param.Unsigned(1, "Frequency divider")