src/arch/x86/regs/float.hh

/*
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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 * this software without specific prior written permission.
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#ifndef __ARCH_X86_FLOATREGS_HH__
#define __ARCH_X86_FLOATREGS_HH__

#include "arch/x86/x86_traits.hh"
#include "base/bitunion.hh"

namespace gem5
{
namespace X86ISA
{
namespace float_reg
{
enum FloatRegIndex
{
    // MMX/X87 registers
    MmxBase,
    FprBase = MmxBase,
    _Mmx0Idx = MmxBase,
    _Mmx1Idx,
    _Mmx2Idx,
    _Mmx3Idx,
    _Mmx4Idx,
    _Mmx5Idx,
    _Mmx6Idx,
    _Mmx7Idx,

    _Fpr0Idx = FprBase,
    _Fpr1Idx,
    _Fpr2Idx,
    _Fpr3Idx,
    _Fpr4Idx,
    _Fpr5Idx,
    _Fpr6Idx,
    _Fpr7Idx,

    XmmBase = MmxBase + NumMMXRegs,
    _Xmm0LowIdx = XmmBase,
    _Xmm0HighIdx,
    _Xmm1LowIdx,
    _Xmm1HighIdx,
    _Xmm2LowIdx,
    _Xmm2HighIdx,
    _Xmm3LowIdx,
    _Xmm3HighIdx,
    _Xmm4LowIdx,
    _Xmm4HighIdx,
    _Xmm5LowIdx,
    _Xmm5HighIdx,
    _Xmm6LowIdx,
    _Xmm6HighIdx,
    _Xmm7LowIdx,
    _Xmm7HighIdx,
    _Xmm8LowIdx,
    _Xmm8HighIdx,
    _Xmm9LowIdx,
    _Xmm9HighIdx,
    _Xmm10LowIdx,
    _Xmm10HighIdx,
    _Xmm11LowIdx,
    _Xmm11HighIdx,
    _Xmm12LowIdx,
    _Xmm12HighIdx,
    _Xmm13LowIdx,
    _Xmm13HighIdx,
    _Xmm14LowIdx,
    _Xmm14HighIdx,
    _Xmm15LowIdx,
    _Xmm15HighIdx,

    MicrofpBase = XmmBase + 2 * NumXMMRegs,
    _Microfp0Idx = MicrofpBase,
    _Microfp1Idx,
    _Microfp2Idx,
    _Microfp3Idx,
    _Microfp4Idx,
    _Microfp5Idx,
    _Microfp6Idx,
    _Microfp7Idx,

    NumRegs = MicrofpBase + NumMicroFpRegs
};

static inline RegId
mmx(int index)
{
    return RegId(FloatRegClass, MmxBase + index);
}

static inline RegId
fpr(int index)
{
    return RegId(FloatRegClass, FprBase + index);
}

static inline RegId
xmm(int index)
{
    return RegId(FloatRegClass, XmmBase + index);
}

static inline RegId
xmmLow(int index)
{
    return RegId(FloatRegClass, XmmBase + 2 * index);
}

static inline RegId
xmmHigh(int index)
{
    return RegId(FloatRegClass, XmmBase + 2 * index + 1);
}

static inline RegId
microfp(int index)
{
    return RegId(FloatRegClass, MicrofpBase + index);
}

static inline RegId
stack(int index, int top)
{
    return fpr((top + index + 8) % 8);
}

} // namespace float_reg

} // namespace X86ISA
} // namespace gem5

#endif // __ARCH_X86_FLOATREGS_HH__