| |
| ---------- Begin Simulation Statistics ---------- |
| sim_seconds 0.147164 |
| sim_ticks 147164058500 |
| final_tick 147164058500 |
| sim_freq 1000000000000 |
| host_inst_rate 652695 |
| host_op_rate 655939 |
| host_tick_rate 1060461195 |
| host_mem_usage 414592 |
| host_seconds 138.77 |
| sim_insts 90576862 |
| sim_ops 91026991 |
| system.voltage_domain.voltage 1 |
| system.clk_domain.clock 1000 |
| system.physmem.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.physmem.bytes_read::cpu.inst 36928 |
| system.physmem.bytes_read::cpu.data 944832 |
| system.physmem.bytes_read::total 981760 |
| system.physmem.bytes_inst_read::cpu.inst 36928 |
| system.physmem.bytes_inst_read::total 36928 |
| system.physmem.num_reads::cpu.inst 577 |
| system.physmem.num_reads::cpu.data 14763 |
| system.physmem.num_reads::total 15340 |
| system.physmem.bw_read::cpu.inst 250931 |
| system.physmem.bw_read::cpu.data 6420263 |
| system.physmem.bw_read::total 6671194 |
| system.physmem.bw_inst_read::cpu.inst 250931 |
| system.physmem.bw_inst_read::total 250931 |
| system.physmem.bw_total::cpu.inst 250931 |
| system.physmem.bw_total::cpu.data 6420263 |
| system.physmem.bw_total::total 6671194 |
| system.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu_clk_domain.clock 500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.dstage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.dstage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.dstage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.hits 0 |
| system.cpu.dstage2_mmu.stage2_tlb.misses 0 |
| system.cpu.dstage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.dtb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.dtb.walker.walks 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.dtb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.dtb.walker.walkRequestOrigin::total 0 |
| system.cpu.dtb.inst_hits 0 |
| system.cpu.dtb.inst_misses 0 |
| system.cpu.dtb.read_hits 0 |
| system.cpu.dtb.read_misses 0 |
| system.cpu.dtb.write_hits 0 |
| system.cpu.dtb.write_misses 0 |
| system.cpu.dtb.flush_tlb 0 |
| system.cpu.dtb.flush_tlb_mva 0 |
| system.cpu.dtb.flush_tlb_mva_asid 0 |
| system.cpu.dtb.flush_tlb_asid 0 |
| system.cpu.dtb.flush_entries 0 |
| system.cpu.dtb.align_faults 0 |
| system.cpu.dtb.prefetch_faults 0 |
| system.cpu.dtb.domain_faults 0 |
| system.cpu.dtb.perms_faults 0 |
| system.cpu.dtb.read_accesses 0 |
| system.cpu.dtb.write_accesses 0 |
| system.cpu.dtb.inst_accesses 0 |
| system.cpu.dtb.hits 0 |
| system.cpu.dtb.misses 0 |
| system.cpu.dtb.accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walks 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.walker.walkRequestOrigin::total 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_mva_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_tlb_asid 0 |
| system.cpu.istage2_mmu.stage2_tlb.flush_entries 0 |
| system.cpu.istage2_mmu.stage2_tlb.align_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.prefetch_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.domain_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.perms_faults 0 |
| system.cpu.istage2_mmu.stage2_tlb.read_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.write_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.inst_accesses 0 |
| system.cpu.istage2_mmu.stage2_tlb.hits 0 |
| system.cpu.istage2_mmu.stage2_tlb.misses 0 |
| system.cpu.istage2_mmu.stage2_tlb.accesses 0 |
| system.cpu.itb.walker.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.itb.walker.walks 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Requested::total 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Data 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::Inst 0 |
| system.cpu.itb.walker.walkRequestOrigin_Completed::total 0 |
| system.cpu.itb.walker.walkRequestOrigin::total 0 |
| system.cpu.itb.inst_hits 0 |
| system.cpu.itb.inst_misses 0 |
| system.cpu.itb.read_hits 0 |
| system.cpu.itb.read_misses 0 |
| system.cpu.itb.write_hits 0 |
| system.cpu.itb.write_misses 0 |
| system.cpu.itb.flush_tlb 0 |
| system.cpu.itb.flush_tlb_mva 0 |
| system.cpu.itb.flush_tlb_mva_asid 0 |
| system.cpu.itb.flush_tlb_asid 0 |
| system.cpu.itb.flush_entries 0 |
| system.cpu.itb.align_faults 0 |
| system.cpu.itb.prefetch_faults 0 |
| system.cpu.itb.domain_faults 0 |
| system.cpu.itb.perms_faults 0 |
| system.cpu.itb.read_accesses 0 |
| system.cpu.itb.write_accesses 0 |
| system.cpu.itb.inst_accesses 0 |
| system.cpu.itb.hits 0 |
| system.cpu.itb.misses 0 |
| system.cpu.itb.accesses 0 |
| system.cpu.workload.numSyscalls 442 |
| system.cpu.pwrStateResidencyTicks::ON 147164058500 |
| system.cpu.numCycles 294328117 |
| system.cpu.numWorkItemsStarted 0 |
| system.cpu.numWorkItemsCompleted 0 |
| system.cpu.committedInsts 90576862 |
| system.cpu.committedOps 91026991 |
| system.cpu.num_int_alu_accesses 72326352 |
| system.cpu.num_fp_alu_accesses 48 |
| system.cpu.num_func_calls 112245 |
| system.cpu.num_conditional_control_insts 15520157 |
| system.cpu.num_int_insts 72326352 |
| system.cpu.num_fp_insts 48 |
| system.cpu.num_int_register_reads 124236934 |
| system.cpu.num_int_register_writes 52782988 |
| system.cpu.num_fp_register_reads 54 |
| system.cpu.num_fp_register_writes 30 |
| system.cpu.num_cc_register_reads 339191621 |
| system.cpu.num_cc_register_writes 53956115 |
| system.cpu.num_mem_refs 27220755 |
| system.cpu.num_load_insts 22475911 |
| system.cpu.num_store_insts 4744844 |
| system.cpu.num_idle_cycles 0 |
| system.cpu.num_busy_cycles 294328117 |
| system.cpu.not_idle_fraction 1 |
| system.cpu.idle_fraction 0 |
| system.cpu.Branches 18732305 |
| system.cpu.op_class::No_OpClass 0 0.00% 0.00% |
| system.cpu.op_class::IntAlu 63822829 70.09% 70.09% |
| system.cpu.op_class::IntMult 10474 0.01% 70.10% |
| system.cpu.op_class::IntDiv 0 0.00% 70.10% |
| system.cpu.op_class::FloatAdd 0 0.00% 70.10% |
| system.cpu.op_class::FloatCmp 0 0.00% 70.10% |
| system.cpu.op_class::FloatCvt 0 0.00% 70.10% |
| system.cpu.op_class::FloatMult 0 0.00% 70.10% |
| system.cpu.op_class::FloatMultAcc 0 0.00% 70.10% |
| system.cpu.op_class::FloatDiv 0 0.00% 70.10% |
| system.cpu.op_class::FloatMisc 0 0.00% 70.10% |
| system.cpu.op_class::FloatSqrt 0 0.00% 70.10% |
| system.cpu.op_class::SimdAdd 0 0.00% 70.10% |
| system.cpu.op_class::SimdAddAcc 0 0.00% 70.10% |
| system.cpu.op_class::SimdAlu 0 0.00% 70.10% |
| system.cpu.op_class::SimdCmp 0 0.00% 70.10% |
| system.cpu.op_class::SimdCvt 0 0.00% 70.10% |
| system.cpu.op_class::SimdMisc 0 0.00% 70.10% |
| system.cpu.op_class::SimdMult 0 0.00% 70.10% |
| system.cpu.op_class::SimdMultAcc 0 0.00% 70.10% |
| system.cpu.op_class::SimdShift 0 0.00% 70.10% |
| system.cpu.op_class::SimdShiftAcc 0 0.00% 70.10% |
| system.cpu.op_class::SimdSqrt 0 0.00% 70.10% |
| system.cpu.op_class::SimdFloatAdd 0 0.00% 70.10% |
| system.cpu.op_class::SimdFloatAlu 0 0.00% 70.10% |
| system.cpu.op_class::SimdFloatCmp 0 0.00% 70.10% |
| system.cpu.op_class::SimdFloatCvt 6 0.00% 70.10% |
| system.cpu.op_class::SimdFloatDiv 0 0.00% 70.10% |
| system.cpu.op_class::SimdFloatMisc 15 0.00% 70.10% |
| system.cpu.op_class::SimdFloatMult 0 0.00% 70.10% |
| system.cpu.op_class::SimdFloatMultAcc 2 0.00% 70.10% |
| system.cpu.op_class::SimdFloatSqrt 0 0.00% 70.10% |
| system.cpu.op_class::MemRead 22475905 24.68% 94.79% |
| system.cpu.op_class::MemWrite 4744822 5.21% 100.00% |
| system.cpu.op_class::FloatMemRead 6 0.00% 100.00% |
| system.cpu.op_class::FloatMemWrite 22 0.00% 100.00% |
| system.cpu.op_class::IprAccess 0 0.00% 100.00% |
| system.cpu.op_class::InstPrefetch 0 0.00% 100.00% |
| system.cpu.op_class::total 91054081 |
| system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.dcache.tags.replacements 942702 |
| system.cpu.dcache.tags.tagsinuse 3565.461526 |
| system.cpu.dcache.tags.total_refs 26253601 |
| system.cpu.dcache.tags.sampled_refs 946798 |
| system.cpu.dcache.tags.avg_refs 27.728830 |
| system.cpu.dcache.tags.warmup_cycle 54459450500 |
| system.cpu.dcache.tags.occ_blocks::cpu.data 3565.461526 |
| system.cpu.dcache.tags.occ_percent::cpu.data 0.870474 |
| system.cpu.dcache.tags.occ_percent::total 0.870474 |
| system.cpu.dcache.tags.occ_task_id_blocks::1024 4096 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::0 118 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::1 1358 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::2 2564 |
| system.cpu.dcache.tags.age_task_id_blocks_1024::3 56 |
| system.cpu.dcache.tags.occ_task_id_percent::1024 1 |
| system.cpu.dcache.tags.tag_accesses 55347598 |
| system.cpu.dcache.tags.data_accesses 55347598 |
| system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.dcache.ReadReq_hits::cpu.data 21556948 |
| system.cpu.dcache.ReadReq_hits::total 21556948 |
| system.cpu.dcache.WriteReq_hits::cpu.data 4688372 |
| system.cpu.dcache.WriteReq_hits::total 4688372 |
| system.cpu.dcache.SoftPFReq_hits::cpu.data 507 |
| system.cpu.dcache.SoftPFReq_hits::total 507 |
| system.cpu.dcache.LoadLockedReq_hits::cpu.data 3887 |
| system.cpu.dcache.LoadLockedReq_hits::total 3887 |
| system.cpu.dcache.StoreCondReq_hits::cpu.data 3887 |
| system.cpu.dcache.StoreCondReq_hits::total 3887 |
| system.cpu.dcache.demand_hits::cpu.data 26245320 |
| system.cpu.dcache.demand_hits::total 26245320 |
| system.cpu.dcache.overall_hits::cpu.data 26245827 |
| system.cpu.dcache.overall_hits::total 26245827 |
| system.cpu.dcache.ReadReq_misses::cpu.data 900187 |
| system.cpu.dcache.ReadReq_misses::total 900187 |
| system.cpu.dcache.WriteReq_misses::cpu.data 46609 |
| system.cpu.dcache.WriteReq_misses::total 46609 |
| system.cpu.dcache.SoftPFReq_misses::cpu.data 3 |
| system.cpu.dcache.SoftPFReq_misses::total 3 |
| system.cpu.dcache.demand_misses::cpu.data 946796 |
| system.cpu.dcache.demand_misses::total 946796 |
| system.cpu.dcache.overall_misses::cpu.data 946799 |
| system.cpu.dcache.overall_misses::total 946799 |
| system.cpu.dcache.ReadReq_miss_latency::cpu.data 11713223000 |
| system.cpu.dcache.ReadReq_miss_latency::total 11713223000 |
| system.cpu.dcache.WriteReq_miss_latency::cpu.data 1333567500 |
| system.cpu.dcache.WriteReq_miss_latency::total 1333567500 |
| system.cpu.dcache.demand_miss_latency::cpu.data 13046790500 |
| system.cpu.dcache.demand_miss_latency::total 13046790500 |
| system.cpu.dcache.overall_miss_latency::cpu.data 13046790500 |
| system.cpu.dcache.overall_miss_latency::total 13046790500 |
| system.cpu.dcache.ReadReq_accesses::cpu.data 22457135 |
| system.cpu.dcache.ReadReq_accesses::total 22457135 |
| system.cpu.dcache.WriteReq_accesses::cpu.data 4734981 |
| system.cpu.dcache.WriteReq_accesses::total 4734981 |
| system.cpu.dcache.SoftPFReq_accesses::cpu.data 510 |
| system.cpu.dcache.SoftPFReq_accesses::total 510 |
| system.cpu.dcache.LoadLockedReq_accesses::cpu.data 3887 |
| system.cpu.dcache.LoadLockedReq_accesses::total 3887 |
| system.cpu.dcache.StoreCondReq_accesses::cpu.data 3887 |
| system.cpu.dcache.StoreCondReq_accesses::total 3887 |
| system.cpu.dcache.demand_accesses::cpu.data 27192116 |
| system.cpu.dcache.demand_accesses::total 27192116 |
| system.cpu.dcache.overall_accesses::cpu.data 27192626 |
| system.cpu.dcache.overall_accesses::total 27192626 |
| system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.040085 |
| system.cpu.dcache.ReadReq_miss_rate::total 0.040085 |
| system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.009844 |
| system.cpu.dcache.WriteReq_miss_rate::total 0.009844 |
| system.cpu.dcache.SoftPFReq_miss_rate::cpu.data 0.005882 |
| system.cpu.dcache.SoftPFReq_miss_rate::total 0.005882 |
| system.cpu.dcache.demand_miss_rate::cpu.data 0.034819 |
| system.cpu.dcache.demand_miss_rate::total 0.034819 |
| system.cpu.dcache.overall_miss_rate::cpu.data 0.034818 |
| system.cpu.dcache.overall_miss_rate::total 0.034818 |
| system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 13011.988620 |
| system.cpu.dcache.ReadReq_avg_miss_latency::total 13011.988620 |
| system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 28611.802442 |
| system.cpu.dcache.WriteReq_avg_miss_latency::total 28611.802442 |
| system.cpu.dcache.demand_avg_miss_latency::cpu.data 13779.938339 |
| system.cpu.dcache.demand_avg_miss_latency::total 13779.938339 |
| system.cpu.dcache.overall_avg_miss_latency::cpu.data 13779.894677 |
| system.cpu.dcache.overall_avg_miss_latency::total 13779.894677 |
| system.cpu.dcache.blocked_cycles::no_mshrs 0 |
| system.cpu.dcache.blocked_cycles::no_targets 0 |
| system.cpu.dcache.blocked::no_mshrs 0 |
| system.cpu.dcache.blocked::no_targets 0 |
| system.cpu.dcache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.dcache.avg_blocked_cycles::no_targets nan |
| system.cpu.dcache.writebacks::writebacks 942334 |
| system.cpu.dcache.writebacks::total 942334 |
| system.cpu.dcache.ReadReq_mshr_hits::cpu.data 1 |
| system.cpu.dcache.ReadReq_mshr_hits::total 1 |
| system.cpu.dcache.demand_mshr_hits::cpu.data 1 |
| system.cpu.dcache.demand_mshr_hits::total 1 |
| system.cpu.dcache.overall_mshr_hits::cpu.data 1 |
| system.cpu.dcache.overall_mshr_hits::total 1 |
| system.cpu.dcache.ReadReq_mshr_misses::cpu.data 900186 |
| system.cpu.dcache.ReadReq_mshr_misses::total 900186 |
| system.cpu.dcache.WriteReq_mshr_misses::cpu.data 46609 |
| system.cpu.dcache.WriteReq_mshr_misses::total 46609 |
| system.cpu.dcache.SoftPFReq_mshr_misses::cpu.data 3 |
| system.cpu.dcache.SoftPFReq_mshr_misses::total 3 |
| system.cpu.dcache.demand_mshr_misses::cpu.data 946795 |
| system.cpu.dcache.demand_mshr_misses::total 946795 |
| system.cpu.dcache.overall_mshr_misses::cpu.data 946798 |
| system.cpu.dcache.overall_mshr_misses::total 946798 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 10812989000 |
| system.cpu.dcache.ReadReq_mshr_miss_latency::total 10812989000 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1286958500 |
| system.cpu.dcache.WriteReq_mshr_miss_latency::total 1286958500 |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::cpu.data 136000 |
| system.cpu.dcache.SoftPFReq_mshr_miss_latency::total 136000 |
| system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12099947500 |
| system.cpu.dcache.demand_mshr_miss_latency::total 12099947500 |
| system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12100083500 |
| system.cpu.dcache.overall_mshr_miss_latency::total 12100083500 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.040085 |
| system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.040085 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.009844 |
| system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.009844 |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::cpu.data 0.005882 |
| system.cpu.dcache.SoftPFReq_mshr_miss_rate::total 0.005882 |
| system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.034819 |
| system.cpu.dcache.demand_mshr_miss_rate::total 0.034819 |
| system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.034818 |
| system.cpu.dcache.overall_mshr_miss_rate::total 0.034818 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 12011.949753 |
| system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 12011.949753 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 27611.802442 |
| system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 27611.802442 |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::cpu.data 45333.333333 |
| system.cpu.dcache.SoftPFReq_avg_mshr_miss_latency::total 45333.333333 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 12779.902196 |
| system.cpu.dcache.demand_avg_mshr_miss_latency::total 12779.902196 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 12780.005344 |
| system.cpu.dcache.overall_avg_mshr_miss_latency::total 12780.005344 |
| system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.icache.tags.replacements 2 |
| system.cpu.icache.tags.tagsinuse 510.110453 |
| system.cpu.icache.tags.total_refs 107830173 |
| system.cpu.icache.tags.sampled_refs 599 |
| system.cpu.icache.tags.avg_refs 180016.983306 |
| system.cpu.icache.tags.warmup_cycle 0 |
| system.cpu.icache.tags.occ_blocks::cpu.inst 510.110453 |
| system.cpu.icache.tags.occ_percent::cpu.inst 0.249077 |
| system.cpu.icache.tags.occ_percent::total 0.249077 |
| system.cpu.icache.tags.occ_task_id_blocks::1024 597 |
| system.cpu.icache.tags.age_task_id_blocks_1024::0 35 |
| system.cpu.icache.tags.age_task_id_blocks_1024::2 6 |
| system.cpu.icache.tags.age_task_id_blocks_1024::3 4 |
| system.cpu.icache.tags.age_task_id_blocks_1024::4 552 |
| system.cpu.icache.tags.occ_task_id_percent::1024 0.291504 |
| system.cpu.icache.tags.tag_accesses 215662143 |
| system.cpu.icache.tags.data_accesses 215662143 |
| system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.icache.ReadReq_hits::cpu.inst 107830173 |
| system.cpu.icache.ReadReq_hits::total 107830173 |
| system.cpu.icache.demand_hits::cpu.inst 107830173 |
| system.cpu.icache.demand_hits::total 107830173 |
| system.cpu.icache.overall_hits::cpu.inst 107830173 |
| system.cpu.icache.overall_hits::total 107830173 |
| system.cpu.icache.ReadReq_misses::cpu.inst 599 |
| system.cpu.icache.ReadReq_misses::total 599 |
| system.cpu.icache.demand_misses::cpu.inst 599 |
| system.cpu.icache.demand_misses::total 599 |
| system.cpu.icache.overall_misses::cpu.inst 599 |
| system.cpu.icache.overall_misses::total 599 |
| system.cpu.icache.ReadReq_miss_latency::cpu.inst 36670000 |
| system.cpu.icache.ReadReq_miss_latency::total 36670000 |
| system.cpu.icache.demand_miss_latency::cpu.inst 36670000 |
| system.cpu.icache.demand_miss_latency::total 36670000 |
| system.cpu.icache.overall_miss_latency::cpu.inst 36670000 |
| system.cpu.icache.overall_miss_latency::total 36670000 |
| system.cpu.icache.ReadReq_accesses::cpu.inst 107830772 |
| system.cpu.icache.ReadReq_accesses::total 107830772 |
| system.cpu.icache.demand_accesses::cpu.inst 107830772 |
| system.cpu.icache.demand_accesses::total 107830772 |
| system.cpu.icache.overall_accesses::cpu.inst 107830772 |
| system.cpu.icache.overall_accesses::total 107830772 |
| system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.000006 |
| system.cpu.icache.ReadReq_miss_rate::total 0.000006 |
| system.cpu.icache.demand_miss_rate::cpu.inst 0.000006 |
| system.cpu.icache.demand_miss_rate::total 0.000006 |
| system.cpu.icache.overall_miss_rate::cpu.inst 0.000006 |
| system.cpu.icache.overall_miss_rate::total 0.000006 |
| system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61218.697830 |
| system.cpu.icache.ReadReq_avg_miss_latency::total 61218.697830 |
| system.cpu.icache.demand_avg_miss_latency::cpu.inst 61218.697830 |
| system.cpu.icache.demand_avg_miss_latency::total 61218.697830 |
| system.cpu.icache.overall_avg_miss_latency::cpu.inst 61218.697830 |
| system.cpu.icache.overall_avg_miss_latency::total 61218.697830 |
| system.cpu.icache.blocked_cycles::no_mshrs 0 |
| system.cpu.icache.blocked_cycles::no_targets 0 |
| system.cpu.icache.blocked::no_mshrs 0 |
| system.cpu.icache.blocked::no_targets 0 |
| system.cpu.icache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.icache.avg_blocked_cycles::no_targets nan |
| system.cpu.icache.writebacks::writebacks 2 |
| system.cpu.icache.writebacks::total 2 |
| system.cpu.icache.ReadReq_mshr_misses::cpu.inst 599 |
| system.cpu.icache.ReadReq_mshr_misses::total 599 |
| system.cpu.icache.demand_mshr_misses::cpu.inst 599 |
| system.cpu.icache.demand_mshr_misses::total 599 |
| system.cpu.icache.overall_mshr_misses::cpu.inst 599 |
| system.cpu.icache.overall_mshr_misses::total 599 |
| system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 36071000 |
| system.cpu.icache.ReadReq_mshr_miss_latency::total 36071000 |
| system.cpu.icache.demand_mshr_miss_latency::cpu.inst 36071000 |
| system.cpu.icache.demand_mshr_miss_latency::total 36071000 |
| system.cpu.icache.overall_mshr_miss_latency::cpu.inst 36071000 |
| system.cpu.icache.overall_mshr_miss_latency::total 36071000 |
| system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.000006 |
| system.cpu.icache.ReadReq_mshr_miss_rate::total 0.000006 |
| system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.000006 |
| system.cpu.icache.demand_mshr_miss_rate::total 0.000006 |
| system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.000006 |
| system.cpu.icache.overall_mshr_miss_rate::total 0.000006 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60218.697830 |
| system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60218.697830 |
| system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60218.697830 |
| system.cpu.icache.demand_avg_mshr_miss_latency::total 60218.697830 |
| system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60218.697830 |
| system.cpu.icache.overall_avg_mshr_miss_latency::total 60218.697830 |
| system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.l2cache.tags.replacements 0 |
| system.cpu.l2cache.tags.tagsinuse 10666.571104 |
| system.cpu.l2cache.tags.total_refs 1874647 |
| system.cpu.l2cache.tags.sampled_refs 15340 |
| system.cpu.l2cache.tags.avg_refs 122.206454 |
| system.cpu.l2cache.tags.warmup_cycle 0 |
| system.cpu.l2cache.tags.occ_blocks::cpu.inst 494.163402 |
| system.cpu.l2cache.tags.occ_blocks::cpu.data 10172.407702 |
| system.cpu.l2cache.tags.occ_percent::cpu.inst 0.015081 |
| system.cpu.l2cache.tags.occ_percent::cpu.data 0.310437 |
| system.cpu.l2cache.tags.occ_percent::total 0.325518 |
| system.cpu.l2cache.tags.occ_task_id_blocks::1024 15340 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::0 42 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::1 4 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::2 59 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::3 6 |
| system.cpu.l2cache.tags.age_task_id_blocks_1024::4 15229 |
| system.cpu.l2cache.tags.occ_task_id_percent::1024 0.468140 |
| system.cpu.l2cache.tags.tag_accesses 15135236 |
| system.cpu.l2cache.tags.data_accesses 15135236 |
| system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.l2cache.WritebackDirty_hits::writebacks 942334 |
| system.cpu.l2cache.WritebackDirty_hits::total 942334 |
| system.cpu.l2cache.WritebackClean_hits::writebacks 1 |
| system.cpu.l2cache.WritebackClean_hits::total 1 |
| system.cpu.l2cache.ReadExReq_hits::cpu.data 32061 |
| system.cpu.l2cache.ReadExReq_hits::total 32061 |
| system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 22 |
| system.cpu.l2cache.ReadCleanReq_hits::total 22 |
| system.cpu.l2cache.ReadSharedReq_hits::cpu.data 899974 |
| system.cpu.l2cache.ReadSharedReq_hits::total 899974 |
| system.cpu.l2cache.demand_hits::cpu.inst 22 |
| system.cpu.l2cache.demand_hits::cpu.data 932035 |
| system.cpu.l2cache.demand_hits::total 932057 |
| system.cpu.l2cache.overall_hits::cpu.inst 22 |
| system.cpu.l2cache.overall_hits::cpu.data 932035 |
| system.cpu.l2cache.overall_hits::total 932057 |
| system.cpu.l2cache.ReadExReq_misses::cpu.data 14548 |
| system.cpu.l2cache.ReadExReq_misses::total 14548 |
| system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 577 |
| system.cpu.l2cache.ReadCleanReq_misses::total 577 |
| system.cpu.l2cache.ReadSharedReq_misses::cpu.data 215 |
| system.cpu.l2cache.ReadSharedReq_misses::total 215 |
| system.cpu.l2cache.demand_misses::cpu.inst 577 |
| system.cpu.l2cache.demand_misses::cpu.data 14763 |
| system.cpu.l2cache.demand_misses::total 15340 |
| system.cpu.l2cache.overall_misses::cpu.inst 577 |
| system.cpu.l2cache.overall_misses::cpu.data 14763 |
| system.cpu.l2cache.overall_misses::total 15340 |
| system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 880404500 |
| system.cpu.l2cache.ReadExReq_miss_latency::total 880404500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 34920500 |
| system.cpu.l2cache.ReadCleanReq_miss_latency::total 34920500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 13009500 |
| system.cpu.l2cache.ReadSharedReq_miss_latency::total 13009500 |
| system.cpu.l2cache.demand_miss_latency::cpu.inst 34920500 |
| system.cpu.l2cache.demand_miss_latency::cpu.data 893414000 |
| system.cpu.l2cache.demand_miss_latency::total 928334500 |
| system.cpu.l2cache.overall_miss_latency::cpu.inst 34920500 |
| system.cpu.l2cache.overall_miss_latency::cpu.data 893414000 |
| system.cpu.l2cache.overall_miss_latency::total 928334500 |
| system.cpu.l2cache.WritebackDirty_accesses::writebacks 942334 |
| system.cpu.l2cache.WritebackDirty_accesses::total 942334 |
| system.cpu.l2cache.WritebackClean_accesses::writebacks 1 |
| system.cpu.l2cache.WritebackClean_accesses::total 1 |
| system.cpu.l2cache.ReadExReq_accesses::cpu.data 46609 |
| system.cpu.l2cache.ReadExReq_accesses::total 46609 |
| system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 599 |
| system.cpu.l2cache.ReadCleanReq_accesses::total 599 |
| system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 900189 |
| system.cpu.l2cache.ReadSharedReq_accesses::total 900189 |
| system.cpu.l2cache.demand_accesses::cpu.inst 599 |
| system.cpu.l2cache.demand_accesses::cpu.data 946798 |
| system.cpu.l2cache.demand_accesses::total 947397 |
| system.cpu.l2cache.overall_accesses::cpu.inst 599 |
| system.cpu.l2cache.overall_accesses::cpu.data 946798 |
| system.cpu.l2cache.overall_accesses::total 947397 |
| system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 0.312129 |
| system.cpu.l2cache.ReadExReq_miss_rate::total 0.312129 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.963272 |
| system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.963272 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 0.000239 |
| system.cpu.l2cache.ReadSharedReq_miss_rate::total 0.000239 |
| system.cpu.l2cache.demand_miss_rate::cpu.inst 0.963272 |
| system.cpu.l2cache.demand_miss_rate::cpu.data 0.015593 |
| system.cpu.l2cache.demand_miss_rate::total 0.016192 |
| system.cpu.l2cache.overall_miss_rate::cpu.inst 0.963272 |
| system.cpu.l2cache.overall_miss_rate::cpu.data 0.015593 |
| system.cpu.l2cache.overall_miss_rate::total 0.016192 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60517.218862 |
| system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60517.218862 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60520.797227 |
| system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60520.797227 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60509.302326 |
| system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60509.302326 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60520.797227 |
| system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60517.103570 |
| system.cpu.l2cache.demand_avg_miss_latency::total 60517.242503 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60520.797227 |
| system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60517.103570 |
| system.cpu.l2cache.overall_avg_miss_latency::total 60517.242503 |
| system.cpu.l2cache.blocked_cycles::no_mshrs 0 |
| system.cpu.l2cache.blocked_cycles::no_targets 0 |
| system.cpu.l2cache.blocked::no_mshrs 0 |
| system.cpu.l2cache.blocked::no_targets 0 |
| system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan |
| system.cpu.l2cache.avg_blocked_cycles::no_targets nan |
| system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 14548 |
| system.cpu.l2cache.ReadExReq_mshr_misses::total 14548 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 577 |
| system.cpu.l2cache.ReadCleanReq_mshr_misses::total 577 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 215 |
| system.cpu.l2cache.ReadSharedReq_mshr_misses::total 215 |
| system.cpu.l2cache.demand_mshr_misses::cpu.inst 577 |
| system.cpu.l2cache.demand_mshr_misses::cpu.data 14763 |
| system.cpu.l2cache.demand_mshr_misses::total 15340 |
| system.cpu.l2cache.overall_mshr_misses::cpu.inst 577 |
| system.cpu.l2cache.overall_mshr_misses::cpu.data 14763 |
| system.cpu.l2cache.overall_mshr_misses::total 15340 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 734924500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 734924500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 29150500 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 29150500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 10859500 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 10859500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 29150500 |
| system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 745784000 |
| system.cpu.l2cache.demand_mshr_miss_latency::total 774934500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 29150500 |
| system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 745784000 |
| system.cpu.l2cache.overall_mshr_miss_latency::total 774934500 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 0.312129 |
| system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 0.312129 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.963272 |
| system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.963272 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 0.000239 |
| system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 0.000239 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.963272 |
| system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.015593 |
| system.cpu.l2cache.demand_mshr_miss_rate::total 0.016192 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.963272 |
| system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.015593 |
| system.cpu.l2cache.overall_mshr_miss_rate::total 0.016192 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50517.218862 |
| system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50517.218862 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50520.797227 |
| system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50520.797227 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50509.302326 |
| system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50509.302326 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50520.797227 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50517.103570 |
| system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50517.242503 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50520.797227 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50517.103570 |
| system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50517.242503 |
| system.cpu.toL2Bus.snoop_filter.tot_requests 1890101 |
| system.cpu.toL2Bus.snoop_filter.hit_single_requests 942715 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_requests 114 |
| system.cpu.toL2Bus.snoop_filter.tot_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 |
| system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 |
| system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.cpu.toL2Bus.trans_dist::ReadResp 900788 |
| system.cpu.toL2Bus.trans_dist::WritebackDirty 942334 |
| system.cpu.toL2Bus.trans_dist::WritebackClean 2 |
| system.cpu.toL2Bus.trans_dist::CleanEvict 368 |
| system.cpu.toL2Bus.trans_dist::ReadExReq 46609 |
| system.cpu.toL2Bus.trans_dist::ReadExResp 46609 |
| system.cpu.toL2Bus.trans_dist::ReadCleanReq 599 |
| system.cpu.toL2Bus.trans_dist::ReadSharedReq 900189 |
| system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 1200 |
| system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 2836298 |
| system.cpu.toL2Bus.pkt_count::total 2837498 |
| system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 38464 |
| system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 120904448 |
| system.cpu.toL2Bus.pkt_size::total 120942912 |
| system.cpu.toL2Bus.snoops 0 |
| system.cpu.toL2Bus.snoopTraffic 0 |
| system.cpu.toL2Bus.snoop_fanout::samples 947397 |
| system.cpu.toL2Bus.snoop_fanout::mean 0.000132 |
| system.cpu.toL2Bus.snoop_fanout::stdev 0.011486 |
| system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.cpu.toL2Bus.snoop_fanout::0 947272 99.99% 99.99% |
| system.cpu.toL2Bus.snoop_fanout::1 125 0.01% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.cpu.toL2Bus.snoop_fanout::min_value 0 |
| system.cpu.toL2Bus.snoop_fanout::max_value 1 |
| system.cpu.toL2Bus.snoop_fanout::total 947397 |
| system.cpu.toL2Bus.reqLayer0.occupancy 1887386500 |
| system.cpu.toL2Bus.reqLayer0.utilization 1.3 |
| system.cpu.toL2Bus.respLayer0.occupancy 898500 |
| system.cpu.toL2Bus.respLayer0.utilization 0.0 |
| system.cpu.toL2Bus.respLayer1.occupancy 1420197000 |
| system.cpu.toL2Bus.respLayer1.utilization 1.0 |
| system.membus.snoop_filter.tot_requests 15340 |
| system.membus.snoop_filter.hit_single_requests 0 |
| system.membus.snoop_filter.hit_multi_requests 0 |
| system.membus.snoop_filter.tot_snoops 0 |
| system.membus.snoop_filter.hit_single_snoops 0 |
| system.membus.snoop_filter.hit_multi_snoops 0 |
| system.membus.pwrStateResidencyTicks::UNDEFINED 147164058500 |
| system.membus.trans_dist::ReadResp 792 |
| system.membus.trans_dist::ReadExReq 14548 |
| system.membus.trans_dist::ReadExResp 14548 |
| system.membus.trans_dist::ReadSharedReq 792 |
| system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 30680 |
| system.membus.pkt_count::total 30680 |
| system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 981760 |
| system.membus.pkt_size::total 981760 |
| system.membus.snoops 0 |
| system.membus.snoopTraffic 0 |
| system.membus.snoop_fanout::samples 15340 |
| system.membus.snoop_fanout::mean 0 |
| system.membus.snoop_fanout::stdev 0 |
| system.membus.snoop_fanout::underflows 0 0.00% 0.00% |
| system.membus.snoop_fanout::0 15340 100.00% 100.00% |
| system.membus.snoop_fanout::1 0 0.00% 100.00% |
| system.membus.snoop_fanout::overflows 0 0.00% 100.00% |
| system.membus.snoop_fanout::min_value 0 |
| system.membus.snoop_fanout::max_value 0 |
| system.membus.snoop_fanout::total 15340 |
| system.membus.reqLayer0.occupancy 15604500 |
| system.membus.reqLayer0.utilization 0.0 |
| system.membus.respLayer1.occupancy 76700000 |
| system.membus.respLayer1.utilization 0.1 |
| |
| ---------- End Simulation Statistics ---------- |
