src/mem/HMCController.py

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from m5.params import *
from m5.objects.XBar import *

# References:
# [1] http://www.open-silicon.com/open-silicon-ips/hmc/
# [2] Ahn, J.; Yoo, S.; Choi, K., "Low-Power Hybrid Memory Cubes With Link
#   Power Management and Two-Level Prefetching," TVLSI 2015

# The HMCController class highlights the fact that a component is required
# between host and HMC to convert the host protocol (AXI for example) to the
# serial links protocol. Moreover, this component should have large internal
# queueing to hide the access latency of the HMC.
# Plus, this controller can implement more advanced global scheduling policies
# and can reorder and steer transactions if required. A good example of such
# component is available in [1].
# Also in [2] there is a similar component which is connected to all serial
# links, and it schedules the requests to the ones which are not busy.
# These two references clarify two things:
# 1. The serial links support the same address range and packets can travel
#  over any of them.
# 2. One host can be connected to more than 1 serial link simply to achieve
#  higher bandwidth, and not for any other reason.

# In this model, we have used a round-robin counter, because it is the
# simplest way to schedule packets over the non-busy serial links. However,
# more advanced scheduling algorithms are possible and even host can dedicate
# each serial link to a portion of the address space and interleave packets
# over them. Yet in this model, we have not made any such assumptions on the
# address space.

class HMCController(NoncoherentXBar):
    type = 'HMCController'
    cxx_header = "mem/hmc_controller.hh"
    cxx_class = 'gem5::HMCController'