mem: Support for separate tRCD and tCL for reads/writes
HBM2 has asynchronous read/write timings (tRCD, tCL). This change
updates dram interface in gem5 to allow using separate values of
tRCD and tCL for reads and writes.
Change-Id: I56bfa9519cedad89cc2d4c163efc7126f609f15a
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59733
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
3 files changed
