commit 84949089a1ff6823c035d1ac84e89e22c96614ed
author Ayaz Akram <yazakram@ucdavis.edu> Sat May 14 00:00:47 2022 -0700
committer Bobby Bruce <bbruce@ucdavis.edu> Mon Jun 06 18:31:06 2022 +0000
tree 8bca3a88f037363d4b646b4c3bbc266e9f4daa1f
parent feceff7723b7b5a23610d22c278a924a47172510

mem: Add HBM2 pseudo channel interface configuration

Change-Id: I5826e50a35ee9dda054a164cfda616ca0ffe82e5
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/59734
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Wendy Elsasser <welsasser@rambus.com>

src/mem/DRAMInterface.py

diff --git a/src/mem/DRAMInterface.py b/src/mem/DRAMInterface.py
index 4fa971a..3d062c3 100644
--- a/src/mem/DRAMInterface.py
+++ b/src/mem/DRAMInterface.py
@@ -1152,6 +1152,87 @@
     # self refresh exit time
     tXS = '65ns'
 
+# A single HBM2 x64 interface (tested with HBMCtrl in gem5)
+# to be used as a single pseudo channel. The timings are based
+# on HBM gen2 specifications. 4H stack, 8Gb per die and total capacity
+# of 4GiB.
+class HBM_2000_4H_1x64(DRAMInterface):
+
+    # 64-bit interface for a single pseudo channel
+    device_bus_width = 64
+
+    # HBM2 supports BL4
+    burst_length = 4
+
+    # size of channel in bytes, 4H stack of 8Gb dies is 4GiB per stack;
+    # with 16 pseudo channels, 256MiB per pseudo channel
+    device_size = "256MiB"
+
+    device_rowbuffer_size = "1KiB"
+
+    # 1x128 configuration
+    devices_per_rank = 1
+
+    ranks_per_channel = 1
+
+    banks_per_rank = 16
+    bank_groups_per_rank = 4
+
+    # 1000 MHz for 2Gbps DDR data rate
+    tCK = "1ns"
+
+    tRP = "14ns"
+
+    tCCD_L = "3ns"
+
+    tRCD = "12ns"
+    tRCD_WR = "6ns"
+    tCL = "18ns"
+    tCWL = "7ns"
+    tRAS = "28ns"
+
+    # BL4 in pseudo channel mode
+    # DDR @ 1000 MHz means 4 * 1ns / 2 = 2ns
+    tBURST = "2ns"
+
+    # value for 2Gb device from JEDEC spec
+    tRFC = "220ns"
+
+    # value for 2Gb device from JEDEC spec
+    tREFI = "3.9us"
+
+    tWR = "14ns"
+    tRTP = "5ns"
+    tWTR = "4ns"
+    tWTR_L = "9ns"
+    tRTW = "18ns"
+
+    #tAAD from RBus
+    tAAD = "1ns"
+
+    # single rank device, set to 0
+    tCS = "0ns"
+
+    tRRD = "4ns"
+    tRRD_L = "6ns"
+
+    # for a single pseudo channel
+    tXAW = "16ns"
+    activation_limit = 4
+
+    # 4tCK
+    tXP = "8ns"
+
+    # start with tRFC + tXP -> 160ns + 8ns = 168ns
+    tXS = "216ns"
+
+    page_policy = 'close_adaptive'
+
+    read_buffer_size = 64
+    write_buffer_size = 64
+
+    two_cycle_activate = True
+
 # A single LPDDR5 x16 interface (one command/address bus)
 # for a single x16 channel with default timings based on
 # initial JEDEC specification

src/mem/HBMCtrl.py

diff --git a/src/mem/HBMCtrl.py b/src/mem/HBMCtrl.py
index 4726661..f711376 100644
--- a/src/mem/HBMCtrl.py
+++ b/src/mem/HBMCtrl.py
@@ -38,6 +38,7 @@
     # HBMCtrl uses the SimpleMemCtlr's interface
     # `dram` as the first pseudo channel, the second
     # pseudo channel interface is following
+    # HBMCtrl has been tested with two HBM_2000_4H_1x64 interfaces
     dram_2 = Param.DRAMInterface("DRAM memory interface")
 
     partitioned_q = Param.Bool(True, "split queues for pseudo channels")