a40950a5c97d484b30922fa60091e04e9efd2a99 - public/gem5

commit	a40950a5c97d484b30922fa60091e04e9efd2a99	[log] [tgz]
author	Gabe Black <gabe.black@gmail.com>	Sun Aug 22 06:04:31 2021 -0700
committer	Gabe Black <gabe.black@gmail.com>	Tue Jun 07 18:26:33 2022 +0000
tree	795d648fde4e81feba28ed7ccfec5927de2b9568
parent	caffb4e1ffcaf3d7e3b842abcfe676a9ad727b24 [diff]

arch,cpu: Remove the idea of a zero register.

This is now handled by using the InvalidRegClass.

Change-Id: If43d8f27cfebc249ec6600847bcfd98c9e94cf40
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/49746
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/arch/arm/isa.cc[diff]
src/arch/mips/isa.cc[diff]
src/arch/power/isa.cc[diff]
src/arch/riscv/isa.cc[diff]
src/arch/sparc/isa.cc[diff]
src/arch/x86/isa.cc[diff]
src/cpu/checker/cpu.cc[diff]
src/cpu/checker/cpu.hh[diff]
src/cpu/checker/cpu_impl.hh[diff]
src/cpu/minor/dyn_inst.cc[diff]
src/cpu/minor/exec_context.hh[diff]
src/cpu/minor/execute.cc[diff]
src/cpu/minor/execute.hh[diff]
src/cpu/minor/lsq.cc[diff]
src/cpu/minor/lsq.hh[diff]
src/cpu/minor/scoreboard.cc[diff]
src/cpu/minor/scoreboard.hh[diff]
src/cpu/o3/cpu.cc[diff]
src/cpu/o3/probe/elastic_trace.cc[diff]
src/cpu/o3/probe/elastic_trace.hh[diff]
src/cpu/o3/regfile.cc[diff]
src/cpu/o3/regfile.hh[diff]
src/cpu/o3/rename_map.cc[diff]
src/cpu/o3/rename_map.hh[diff]
src/cpu/o3/scoreboard.cc[diff]
src/cpu/o3/scoreboard.hh[diff]
src/cpu/reg_class.hh[diff]
src/cpu/simple/base.cc[diff]
src/cpu/simple/base.hh[diff]
src/cpu/simple_thread.hh[diff]

30 files changed

tree: 795d648fde4e81feba28ed7ccfec5927de2b9568