commit 87c2f36fa831b9530f4ad0ff7f8f2d91ae534de6
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Jun 08 16:21:49 2022 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Jun 08 21:58:27 2022 +0000
tree cf46716da149fe1f3aa03eb8ddf2d42612a5f064
parent 02ed53ff6b19c4539ce0c21a2dc336d2aa3d4b28

cpu: Fix InvalidRegClass access in CheckerCPU

This is fixing long regressions:

https://jenkins.gem5.org/job/nightly/252/console

Change-Id: Ica56b950e5091d3357060f566e02195cc8136924
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/60449
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>

src/cpu/checker/cpu.hh

diff --git a/src/cpu/checker/cpu.hh b/src/cpu/checker/cpu.hh
index b5fdc64..c455cf5 100644
--- a/src/cpu/checker/cpu.hh
+++ b/src/cpu/checker/cpu.hh
@@ -176,7 +176,10 @@
     RegVal
     getRegOperand(const StaticInst *si, int idx) override
     {
-        return thread->getReg(si->srcRegIdx(idx));
+        const RegId& id = si->srcRegIdx(idx);
+        if (id.is(InvalidRegClass))
+            return 0;
+        return thread->getReg(id);
     }
 
     void