)]}' { "commit": "8899291db656dfbb53df8ad4e4e45da1c3b6d797", "tree": "c8c52ffb313a206925484cccb711d2842ad97fca", "parents": [ "91cd599f058e6891acf93ed5e119c93500a5ecba" ], "author": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Sun Oct 30 12:00:04 2022 -0700" }, "committer": { "name": "Matthew Poremba", "email": "matthew.poremba@amd.com", "time": "Tue Nov 01 15:34:08 2022 +0000" }, "message": "dev-amdgpu: Fix interrupt handler address assignment\n\nThe interrupt handler\u0027s base address is sent via MMIO and must be\nshifted by 8 bits to convert to a byte address. The current code is\nshifting the MMIO dword first then assigning, resulting in the top 8\nbits being shifted out.\n\nThis changeset fixes the issue by assigning the dword to the 64-bit\naddress first then shifting after. Similarly, the upper dword is cast to\na 64-bit value first before shifting.\n\nThis fixes some \"fence fallback timeout\" errors in the m5term output.\nThese timeouts become a problem because the driver will reset after a\nfew hundred of them, killing any running GPU applications as part of the\nprocess.\n\nChange-Id: I0beec313f533765c94063bcf4de8c65aacf2986b\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65092\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\nReviewed-by: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\nMaintainer: Matt Sinclair \u003cmattdsinclair@gmail.com\u003e\n", "tree_diff": [ { "type": "modify", "old_id": "585c1cfc049ebbcfab28a397f5ced2a5e6654d63", "old_mode": 33188, "old_path": "src/dev/amdgpu/interrupt_handler.cc", "new_id": "a771976d98bc6dfd514601328f92db881bcbdbab", "new_mode": 33188, "new_path": "src/dev/amdgpu/interrupt_handler.cc" } ] }