commit 8ec72b4fba82ddd2c5888dd72db5ed54438962bf
author Giacomo Travaglini <giacomo.travaglini@arm.com> Wed Aug 14 17:50:06 2019 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> Tue Aug 20 12:22:51 2019 +0000
tree cdd21540788eed23bea7c2e0a95aa6c6a873bcc9
parent 705fe5ef44a99bc58363e95fd93f88bc5d76143e

dev-arm: Add GITS_PIDR2 register to the ITS memory map

The GITS Peripheral Identification Register #2 bits assignments are the
same as those for GICD_PIDR2.

Change-Id: I235008a383e08dd557d899cb3aa18202ef943f8b
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/20254
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>