src/arch/riscv/stacktrace.hh

/*
 * Copyright (c) 2005 The Regents of The University of Michigan
 * Copyright (c) 2007-2008 The Florida State University
 * Copyright (c) 2009 The University of Edinburgh
 * All rights reserved.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
 *
 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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 */

#ifndef __ARCH_RISCV_STACKTRACE_HH__
#define __ARCH_RISCV_STACKTRACE_HH__

#include "base/logging.hh"
#include "cpu/profile.hh"

namespace gem5
{

namespace RiscvISA
{

class StackTrace : public BaseStackTrace
{
  protected:
    void
    trace(ThreadContext *tc, bool is_call) override
    {
        panic("StackTrace::trace not implemented.");
    }
};

} // namespace RiscvISA
} // namespace gem5

#endif // __ARCH_RISCV_STACKTRACE_HH__