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// -*- mode:c++ -*-
// Copyright (c) 2010-2014, 2016-2018, 2021-2022 Arm Limited
// All rights reserved
//
// The license below extends only to copyright in the software and shall
// not be construed as granting a license to any other intellectual
// property including but not limited to intellectual property relating
// to a hardware implementation of the functionality of the software
// licensed hereunder. You may use the software subject to the license
// terms below provided that you ensure that this notice is replicated
// unmodified and in its entirety in all distributions of the software,
// modified or unmodified, in source code or in binary form.
//
// Copyright (c) 2007-2008 The Florida State University
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are
// met: redistributions of source code must retain the above copyright
// notice, this list of conditions and the following disclaimer;
// redistributions in binary form must reproduce the above copyright
// notice, this list of conditions and the following disclaimer in the
// documentation and/or other materials provided with the distribution;
// neither the name of the copyright holders nor the names of its
// contributors may be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
// "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
// LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
// A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
// OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
// SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
// DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
// THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
// OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
def operand_types {{
'sb' : 'int8_t',
'ub' : 'uint8_t',
'sh' : 'int16_t',
'uh' : 'uint16_t',
'sw' : 'int32_t',
'uw' : 'uint32_t',
'sd' : 'int64_t',
'ud' : 'uint64_t',
'pint' : 'ArmISA::PackedIntReg',
'sq' : '__int128_t',
'uq' : '__uint128_t',
'tud' : 'std::array<uint64_t, 2>',
'sf' : 'float',
'df' : 'double',
'vc' : 'ArmISA::VecRegContainer',
# For operations that are implemented as a template
'x' : 'TPElem',
'xs' : 'TPSElem',
'xd' : 'TPDElem',
'pc' : 'ArmISA::VecPredRegContainer',
'pb' : 'uint8_t'
}};
let {{
cntrlNsBankedWrite = '''
xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()), %(final_val)s)
'''
#PCState operands need to have a sorting index (the number at the end)
#less than all the integer registers which might update the PC. That way
#if the flag bits of the pc state are updated and a branch happens through
#R15, the updates are layered properly and the R15 update isn't lost.
srtNormal = 5
srtCpsr = 4
srtBase = 3
srtPC = 2
srtMode = 1
srtEPC = 0
class VectorElem(VecElemOp):
def __init__(self, idx):
flat_idx = f'((({idx}) / 4) * NumVecElemPerVecReg) + ({idx}) % 4'
super().__init__('sf', flat_idx, 'IsVectorElem', srtNormal)
class VectorReg(VecRegOp):
def __init__(self, idx, base, suffix=''):
elems = {
base + 'P0' + suffix : ('0', 'sf'),
base + 'P1' + suffix : ('1', 'sf'),
base + 'P2' + suffix : ('2', 'sf'),
base + 'P3' + suffix : ('3', 'sf'),
base + 'S' + suffix : ('0', 'sf'),
base + 'D' + suffix : ('0', 'df'),
base + 'Q' + suffix : ('0', 'tud')
}
super().__init__('vc', (idx, elems), 'IsVector', srtNormal)
class VecPredReg(VecPredRegOp):
def __init__(self, idx):
super().__init__('pc', idx, sort_pri=srtNormal)
class IntRegNPC(IntRegOp):
@overrideInOperand
def regId(self):
return f'gem5::ArmISA::couldBeZero({self.reg_spec}) ? RegId() : ' \
f'RegId({self.reg_class}, {self.reg_spec})'
def __init__(self, idx, ctype='uw', id=srtNormal):
super().__init__(ctype, idx, 'IsInteger', id)
class IntReg(IntRegNPC):
@overrideInOperand
def makeRead(self):
'''Maybe PC read'''
return f'{self.base_name} = ({self.reg_spec} == int_reg::Pc) ? ' \
f'readPC(xc) : xc->getRegOperand(' \
f'this, {self.src_reg_idx});\n'
@overrideInOperand
def makeWrite(self):
'''Maybe PC write'''
return f'''
if ({self.reg_spec} == int_reg::Pc)
setNextPC(xc, {self.base_name});
else
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
if (traceData)
traceData->setData({self.base_name});
'''
class PIntReg(IntReg):
def __init__(self, idx):
super().__init__(idx, ctype='pint')
class IntRegAPC(IntReg):
@overrideInOperand
def makeRead(self):
'''Maybe aligned PC read'''
return f'{self.base_name} = ({self.reg_spec} == int_reg::Pc) ? ' \
f'(roundDown(readPC(xc), 4)) : ' \
f'xc->getRegOperand(this, {self.src_reg_idx});\n'
class IntRegIWPC(IntReg):
@overrideInOperand
def makeWrite(self):
'''Maybe interworking PC write'''
return f'''
if ({self.reg_spec} == int_reg::Pc)
setIWNextPC(xc, {self.base_name});
else
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
if (traceData)
traceData->setData({self.base_name});
'''
class IntRegAIWPC(IntReg):
@overrideInOperand
def makeWrite(self):
'''Maybe aligned interworking PC write'''
return f'''
if ({self.reg_spec} == int_reg::Pc) {"{"}
if ((bool)THUMB)
setNextPC(xc, {self.base_name});
else
setIWNextPC(xc, {self.base_name});
{"}"} else {"{"}
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name});
{"}"}
if (traceData)
traceData->setData({self.base_name});
'''
class IntReg64(IntRegOp):
@overrideInOperand
def regId(self):
return f'gem5::ArmISA::couldBeZero({self.reg_spec}) ? RegId() : ' \
f'RegId({self.reg_class}, {self.reg_spec})'
@overrideInOperand
def makeRead(self):
'''aarch64 read'''
return f'{self.base_name} = ' \
f'(xc->getRegOperand(this, {self.src_reg_idx})) & ' \
f'mask(intWidth);\n'
@overrideInOperand
def makeWrite(self):
'''aarch64 write'''
return f'''
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(intWidth));
if (traceData)
traceData->setData({self.base_name});
'''
def __init__(self, idx, id=srtNormal):
super().__init__('ud', idx, 'IsInteger', id)
class IntRegX64(IntReg64):
@overrideInOperand
def makeRead(self):
'''Maybe masked to 32 bit read'''
return f'{self.base_name} = ' \
f'(xc->getRegOperand(this, {self.src_reg_idx}) & ' \
'mask(aarch64 ? 64 : 32));\n'
@overrideInOperand
def makeWrite(self):
'''Maybe masked to 32 bit write'''
return f'''
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(aarch64 ? 64 : 32));
if (traceData)
traceData->setData({self.base_name});
'''
class IntRegW64(IntReg64):
@overrideInOperand
def makeRead(self):
'''Masked to 32 bit read'''
return f'{self.base_name} = ' \
f'(xc->getRegOperand(this, {self.src_reg_idx})) & ' \
f'mask(32);\n'
@overrideInOperand
def makeWrite(self):
'''Masked to 32 bit write'''
return f'''
xc->setRegOperand(this, {self.dest_reg_idx}, {self.base_name} &
mask(32));
if (traceData)
traceData->setData({self.base_name});
'''
class CCReg(CCRegOp):
def __init__(self, idx):
super().__init__('uw', idx, sort_pri=srtNormal)
class CntrlReg(ControlRegOp):
def __init__(self, idx, id=srtNormal, ctype='uw', flags=None):
super().__init__(ctype, idx, flags, id)
class CntrlReg64(CntrlReg):
def __init__(self, idx, id=srtNormal, ctype='ud'):
super().__init__(idx, id, ctype)
class CntrlNsBankedReg(CntrlReg):
@overrideInOperand
def makeRead(self):
return f'{self.base_name} = ' \
f'xc->readMiscReg(snsBankedIndex(op1, xc->tcBase()));\n'
@overrideInOperand
def makeWrite(self):
return f'''
xc->setMiscReg(snsBankedIndex(dest, xc->tcBase()),
{self.base_name});
if (traceData)
traceData->setData({self.base_name});
'''
def __init__(self, idx, id=srtNormal, ctype='uw'):
super().__init__(idx, id, ctype, (None, None, 'IsControl'))
class CntrlNsBankedReg64(CntrlNsBankedReg):
def __init__(self, idx, id=srtNormal, ctype='ud'):
super().__init__(idx, id, ctype)
class CntrlRegNC(CntrlReg):
pass
class PCStateReg(PCStateOp):
def __init__(self, idx, id):
super().__init__('ud', idx, (None, None, 'IsControl'), id)
}};
def operands {{
#Abstracted integer reg operands
'Dest': IntReg('dest'),
'Dest64': IntReg64('dest'),
'XDest': IntRegX64('dest'),
'WDest': IntRegW64('dest'),
'IWDest': IntRegIWPC('dest'),
'AIWDest': IntRegAIWPC('dest'),
'Dest2': IntReg('dest2'),
'XDest2': IntRegX64('dest2'),
'IWDest2': IntRegIWPC('dest2'),
'Result': IntReg('result'),
'XResult': IntRegX64('result'),
'XResult2': IntRegX64('result2'),
'XBase': IntRegX64('base', id=srtBase),
'Base': IntRegAPC('base', id=srtBase),
'XOffset': IntRegX64('offset'),
'Index': IntReg('index'),
'Shift': IntReg('shift'),
'Op1': IntReg('op1'),
'Op2': IntReg('op2'),
'Op3': IntReg('op3'),
'Op164': IntReg64('op1'),
'Op264': IntReg64('op2'),
'Op364': IntReg64('op3'),
'XOp1': IntRegX64('op1'),
'XOp2': IntRegX64('op2'),
'XOp3': IntRegX64('op3'),
'WOp1': IntRegW64('op1'),
'WOp2': IntRegW64('op2'),
'WOp3': IntRegW64('op3'),
'Reg0': IntReg('reg0'),
'Reg1': IntReg('reg1'),
'Reg2': IntReg('reg2'),
'Reg3': IntReg('reg3'),
'PInt0': PIntReg('reg0'),
'PInt1': PIntReg('reg1'),
'PInt2': PIntReg('reg2'),
'PInt3': PIntReg('reg3'),
#Fixed index integer reg operands
'SpMode': IntRegNPC('int_reg::regInMode((OperatingMode)regMode, '
'int_reg::Sp)'),
'DecodedBankedIntReg':
IntRegNPC('decodeMrsMsrBankedIntRegIndex(byteMask, r)'),
'LR': IntRegNPC('int_reg::Lr'),
'XLR': IntRegX64('int_reg::X30'),
'R7': IntRegNPC('7'),
# First four arguments are passed in registers
'R0': IntRegNPC('0'),
'R1': IntRegNPC('1'),
'R2': IntRegNPC('2'),
'R3': IntRegNPC('3'),
'R4': IntRegNPC('4'),
'R5': IntRegNPC('5'),
'X0': IntRegX64('0'),
'X1': IntRegX64('1'),
'X2': IntRegX64('2'),
'X3': IntRegX64('3'),
'X4': IntRegX64('4'),
'X5': IntRegX64('5'),
# Condition code registers
'CondCodesNZ': CCReg('cc_reg::Nz'),
'CondCodesC': CCReg('cc_reg::C'),
'CondCodesV': CCReg('cc_reg::V'),
'CondCodesGE': CCReg('cc_reg::Ge'),
'OptCondCodesNZ': CCReg(
'''((condCode == COND_AL || condCode == COND_UC ||
condCode == COND_CC || condCode == COND_CS ||
condCode == COND_VS || condCode == COND_VC) ?
cc_reg::Zero : cc_reg::Nz)'''),
'OptCondCodesC': CCReg(
'''((condCode == COND_HI || condCode == COND_LS ||
condCode == COND_CS || condCode == COND_CC) ?
cc_reg::C : cc_reg::Zero)'''),
'OptShiftRmCondCodesC': CCReg(
'''((condCode == COND_HI || condCode == COND_LS ||
condCode == COND_CS || condCode == COND_CC ||
shiftType == ROR) ?
cc_reg::C : cc_reg::Zero)'''),
'OptCondCodesV': CCReg(
'''((condCode == COND_VS || condCode == COND_VC ||
condCode == COND_GE || condCode == COND_LT ||
condCode == COND_GT || condCode == COND_LE) ?
cc_reg::V : cc_reg::Zero)'''),
'FpCondCodes': CCReg('cc_reg::Fp'),
#Abstracted floating point reg operands
'FpDest': VectorElem('dest'),
'FpDestP0': VectorElem('dest + 0'),
'FpDestP1': VectorElem('dest + 1'),
'FpDestP2': VectorElem('dest + 2'),
'FpDestP3': VectorElem('dest + 3'),
'FpDestP4': VectorElem('dest + 4'),
'FpDestP5': VectorElem('dest + 5'),
'FpDestP6': VectorElem('dest + 6'),
'FpDestP7': VectorElem('dest + 7'),
'FpDestS0P0': VectorElem('dest + step * 0 + 0'),
'FpDestS0P1': VectorElem('dest + step * 0 + 1'),
'FpDestS1P0': VectorElem('dest + step * 1 + 0'),
'FpDestS1P1': VectorElem('dest + step * 1 + 1'),
'FpDestS2P0': VectorElem('dest + step * 2 + 0'),
'FpDestS2P1': VectorElem('dest + step * 2 + 1'),
'FpDestS3P0': VectorElem('dest + step * 3 + 0'),
'FpDestS3P1': VectorElem('dest + step * 3 + 1'),
'FpDest2': VectorElem('dest2'),
'FpDest2P0': VectorElem('dest2 + 0'),
'FpDest2P1': VectorElem('dest2 + 1'),
'FpDest2P2': VectorElem('dest2 + 2'),
'FpDest2P3': VectorElem('dest2 + 3'),
'FpOp1': VectorElem('op1'),
'FpOp1P0': VectorElem('op1 + 0'),
'FpOp1P1': VectorElem('op1 + 1'),
'FpOp1P2': VectorElem('op1 + 2'),
'FpOp1P3': VectorElem('op1 + 3'),
'FpOp1P4': VectorElem('op1 + 4'),
'FpOp1P5': VectorElem('op1 + 5'),
'FpOp1P6': VectorElem('op1 + 6'),
'FpOp1P7': VectorElem('op1 + 7'),
'FpOp1S0P0': VectorElem('op1 + step * 0 + 0'),
'FpOp1S0P1': VectorElem('op1 + step * 0 + 1'),
'FpOp1S1P0': VectorElem('op1 + step * 1 + 0'),
'FpOp1S1P1': VectorElem('op1 + step * 1 + 1'),
'FpOp1S2P0': VectorElem('op1 + step * 2 + 0'),
'FpOp1S2P1': VectorElem('op1 + step * 2 + 1'),
'FpOp1S3P0': VectorElem('op1 + step * 3 + 0'),
'FpOp1S3P1': VectorElem('op1 + step * 3 + 1'),
'FpOp2': VectorElem('op2'),
'FpOp2P0': VectorElem('op2 + 0'),
'FpOp2P1': VectorElem('op2 + 1'),
'FpOp2P2': VectorElem('op2 + 2'),
'FpOp2P3': VectorElem('op2 + 3'),
# Create AArch64 unpacked view of the FP registers
# Name ::= 'AA64Vec' OpSpec [LaneSpec]
# OpSpec ::= IOSpec [Index] [Plus]
# IOSpec ::= 'S' | 'D'
# Index ::= '0' | ... | '9'
# Plus ::= [PlusAmount] ['l']
# PlusAmount ::= 'p' [PlusAmount]
# LaneSpec ::= 'L' Index
#
# All the constituents are hierarchically defined as part of the Vector
# Register they belong to
'AA64FpOp1': VectorReg('op1', 'AA64FpOp1'),
'AA64FpOp2': VectorReg('op2', 'AA64FpOp2'),
'AA64FpOp3': VectorReg('op3', 'AA64FpOp3'),
'AA64FpDest': VectorReg('dest', 'AA64FpDest'),
'AA64FpDest2': VectorReg('dest2', 'AA64FpDest2'),
'AA64FpOp1V0': VectorReg('op1', 'AA64FpOp1', 'V0'),
'AA64FpOp1V1': VectorReg('op1 + 1', 'AA64FpOp1', 'V1'),
'AA64FpOp1V2': VectorReg('op1 + 2', 'AA64FpOp1', 'V2'),
'AA64FpOp1V3': VectorReg('op1 + 3', 'AA64FpOp1', 'V3'),
'AA64FpOp1V0S': VectorReg('(op1 + 0) % 32', 'AA64FpOp1', 'V0S'),
'AA64FpOp1V1S': VectorReg('(op1 + 1) % 32', 'AA64FpOp1', 'V1S'),
'AA64FpOp1V2S': VectorReg('(op1 + 2) % 32', 'AA64FpOp1', 'V2S'),
'AA64FpOp1V3S': VectorReg('(op1 + 3) % 32', 'AA64FpOp1', 'V3S'),
'AA64FpDestV0': VectorReg('(dest + 0)', 'AA64FpDest', 'V0'),
'AA64FpDestV1': VectorReg('(dest + 1)', 'AA64FpDest', 'V1'),
'AA64FpDestV0L': VectorReg('(dest + 0) % 32', 'AA64FpDest', 'V0L'),
'AA64FpDestV1L': VectorReg('(dest + 1) % 32', 'AA64FpDest', 'V1L'),
# Temporary registers for SVE interleaving
'AA64IntrlvReg0': VectorReg('INTRLVREG0', 'AA64FpIntrlvReg0'),
'AA64IntrlvReg1': VectorReg('INTRLVREG1', 'AA64FpIntrlvReg1'),
'AA64IntrlvReg2': VectorReg('INTRLVREG2', 'AA64FpIntrlvReg2'),
'AA64IntrlvReg3': VectorReg('INTRLVREG3', 'AA64FpIntrlvReg3'),
'AA64FpDestMerge': VectorReg('dest', 'AA64FpDestMerge'),
'AA64FpBase': VectorReg('base', 'AA64FpBase'),
'AA64FpOffset': VectorReg('offset', 'AA64FpOffset'),
'AA64FpUreg0': VectorReg('VECREG_UREG0', 'AA64FpUreg0'),
# Predicate register operands
'GpOp': VecPredReg('gp'),
'POp1': VecPredReg('op1'),
'POp2': VecPredReg('op2'),
'PDest': VecPredReg('dest'),
'PDestMerge': VecPredReg('dest'),
'Ffr': VecPredReg('PREDREG_FFR'),
'FfrAux': VecPredReg('PREDREG_FFR'),
'PUreg0': VecPredReg('PREDREG_UREG0'),
#Abstracted control reg operands
'MiscDest': CntrlReg('dest'),
'MiscOp1': CntrlReg('op1'),
'MiscNsBankedDest': CntrlNsBankedReg('dest'),
'MiscNsBankedOp1': CntrlNsBankedReg('op1'),
'MiscNsBankedDest64': CntrlNsBankedReg64('dest'),
'MiscNsBankedOp164': CntrlNsBankedReg64('op1'),
#Fixed index control regs
'Cpsr': CntrlReg('MISCREG_CPSR', srtCpsr),
'CpsrQ': CntrlReg('MISCREG_CPSR_Q', srtCpsr),
'Spsr': CntrlRegNC('MISCREG_SPSR'),
'Fpsr': CntrlRegNC('MISCREG_FPSR'),
'Fpsid': CntrlRegNC('MISCREG_FPSID'),
'Fpscr': CntrlRegNC('MISCREG_FPSCR'),
'FpscrQc': CntrlRegNC('MISCREG_FPSCR_QC'),
'FpscrExc': CntrlRegNC('MISCREG_FPSCR_EXC'),
'Cpacr': CntrlReg('MISCREG_CPACR'),
'Cpacr64': CntrlReg64('MISCREG_CPACR_EL1'),
'Fpexc': CntrlRegNC('MISCREG_FPEXC'),
'Nsacr': CntrlReg('MISCREG_NSACR'),
'ElrHyp': CntrlRegNC('MISCREG_ELR_HYP'),
'Hcr': CntrlReg('MISCREG_HCR'),
'Hcr64': CntrlReg64('MISCREG_HCR_EL2'),
'CptrEl264': CntrlReg64('MISCREG_CPTR_EL2'),
'CptrEl364': CntrlReg64('MISCREG_CPTR_EL3'),
'Hstr': CntrlReg('MISCREG_HSTR'),
'Scr': CntrlReg('MISCREG_SCR'),
'Scr64': CntrlReg64('MISCREG_SCR_EL3'),
'Sctlr': CntrlRegNC('MISCREG_SCTLR'),
'SevMailbox': CntrlRegNC('MISCREG_SEV_MAILBOX'),
'LLSCLock': CntrlRegNC('MISCREG_LOCKFLAG'),
'Dczid' : CntrlRegNC('MISCREG_DCZID_EL0'),
'PendingDvm': CntrlRegNC('MISCREG_TLBINEEDSYNC'),
#Register fields for microops
'URa' : IntReg('ura'),
'XURa' : IntRegX64('ura'),
'WURa' : IntRegW64('ura'),
'IWRa' : IntRegIWPC('ura'),
'Fa' : VectorElem('ura'),
'URb' : IntReg('urb'),
'XURb' : IntRegX64('urb'),
'URc' : IntReg('urc'),
'XURc' : IntRegX64('urc'),
#Memory Operand
'Mem': MemOp('uw', None, (None, 'IsLoad', 'IsStore'), srtNormal),
#PCState fields
'RawPC': PCStateReg('pc', srtPC),
'PC': PCStateReg('instPC', srtPC),
'NPC': PCStateReg('instNPC', srtPC),
'pNPC': PCStateReg('instNPC', srtEPC),
'IWNPC': PCStateReg('instIWNPC', srtPC),
'Thumb': PCStateReg('thumb', srtPC),
'NextThumb': PCStateReg('nextThumb', srtMode),
'NextJazelle': PCStateReg('nextJazelle', srtMode),
'NextItState': PCStateReg('nextItstate', srtMode),
'Itstate': PCStateReg('itstate', srtMode),
'NextAArch64': PCStateReg('nextAArch64', srtMode),
#Register operands depending on a field in the instruction encoding. These
#should be avoided since they may not be portable across different
#encodings of the same instruction.
'Rd': IntReg('RD'),
'Rm': IntReg('RM'),
'Rs': IntReg('RS'),
'Rn': IntReg('RN'),
'Rt': IntReg('RT')
}};