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# Copyright (c) 2013 ARM Limited
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from m5.params import *
from m5.objects.AbstractMemory import *
# A wrapper for DRAMSim2 multi-channel memory controller
class DRAMSim2(AbstractMemory):
type = 'DRAMSim2'
cxx_header = "mem/dramsim2.hh"
# A single port for now
port = ResponsePort("This port sends responses and receives requests")
deviceConfigFile = Param.String("ini/DDR3_micron_32M_8B_x8_sg15.ini",
"Device configuration file")
systemConfigFile = Param.String("system.ini.example",
"Memory organisation configuration file")
filePath = Param.String("ext/dramsim2/DRAMSim2/",
"Directory to prepend to file names")
traceFile = Param.String("", "Output file for trace generation")
enableDebug = Param.Bool(False, "Enable DRAMSim2 debug output")