/*
 * Copyright (c) 2020 Inria
 * Copyright (c) 2019,2021 ARM Limited
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 * Copyright (c) 1999-2008 Mark D. Hill and David A. Wood
 * All rights reserved.
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 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
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#include "mem/ruby/network/simple/Switch.hh"

#include <numeric>

#include "base/cast.hh"
#include "base/stl_helpers.hh"
#include "mem/ruby/network/MessageBuffer.hh"
#include "mem/ruby/network/simple/SimpleNetwork.hh"

using m5::stl_helpers::operator<<;

Switch::Switch(const Params &p)
  : BasicRouter(p),
    perfectSwitch(m_id, this, p.virt_nets), m_num_connected_buffers(0),
    switchStats(this)
{
    m_port_buffers.reserve(p.port_buffers.size());
    for (auto& buffer : p.port_buffers) {
        m_port_buffers.emplace_back(buffer);
    }
}

void
Switch::init()
{
    BasicRouter::init();
    perfectSwitch.init(m_network_ptr);
}

void
Switch::addInPort(const std::vector<MessageBuffer*>& in)
{
    perfectSwitch.addInPort(in);
}

void
Switch::addOutPort(const std::vector<MessageBuffer*>& out,
                   const NetDest& routing_table_entry,
                   Cycles link_latency, int bw_multiplier)
{
    // Create a throttle
    throttles.emplace_back(m_id, m_network_ptr->params().ruby_system,
        throttles.size(), link_latency, bw_multiplier,
        m_network_ptr->getEndpointBandwidth(), this);

    // Create one buffer per vnet (these are intermediaryQueues)
    std::vector<MessageBuffer*> intermediateBuffers;

    for (int i = 0; i < out.size(); ++i) {
        assert(m_num_connected_buffers < m_port_buffers.size());
        MessageBuffer* buffer_ptr =
            m_port_buffers[m_num_connected_buffers];
        m_num_connected_buffers++;
        intermediateBuffers.push_back(buffer_ptr);
    }

    // Hook the queues to the PerfectSwitch
    perfectSwitch.addOutPort(intermediateBuffers, routing_table_entry);

    // Hook the queues to the Throttle
    throttles.back().addLinks(intermediateBuffers, out);
}

void
Switch::regStats()
{
    BasicRouter::regStats();

    for (auto& throttle : throttles) {
        throttle.regStats();
    }

    for (const auto& throttle : throttles) {
        switchStats.m_avg_utilization += throttle.getUtilization();
    }
    switchStats.m_avg_utilization /= Stats::constant(throttles.size());

    for (unsigned int type = MessageSizeType_FIRST;
         type < MessageSizeType_NUM; ++type) {
        switchStats.m_msg_counts[type] = new Stats::Formula(&switchStats,
            csprintf("msg_count.%s",
                MessageSizeType_to_string(MessageSizeType(type))).c_str());
        switchStats.m_msg_counts[type]
            ->flags(Stats::nozero)
            ;

        switchStats.m_msg_bytes[type] = new Stats::Formula(&switchStats,
            csprintf("msg_bytes.%s",
                MessageSizeType_to_string(MessageSizeType(type))).c_str());
        switchStats.m_msg_bytes[type]
            ->flags(Stats::nozero)
            ;

        for (const auto& throttle : throttles) {
            *(switchStats.m_msg_counts[type]) += throttle.getMsgCount(type);
        }
        *(switchStats.m_msg_bytes[type]) =
            *(switchStats.m_msg_counts[type]) * Stats::constant(
                Network::MessageSizeType_to_int(MessageSizeType(type)));
    }
}

void
Switch::resetStats()
{
    perfectSwitch.clearStats();
    for (auto& throttle : throttles) {
        throttle.clearStats();
    }
}

void
Switch::collateStats()
{
    perfectSwitch.collateStats();
    for (auto& throttle : throttles) {
        throttle.collateStats();
    }
}

void
Switch::print(std::ostream& out) const
{
    // FIXME printing
    out << "[Switch]";
}

bool
Switch::functionalRead(Packet *pkt)
{
    for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
        if (m_port_buffers[i]->functionalRead(pkt))
            return true;
    }
    return false;
}

bool
Switch::functionalRead(Packet *pkt, WriteMask &mask)
{
    bool read = false;
    for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
        if (m_port_buffers[i]->functionalRead(pkt, mask))
            read = true;
    }
    return read;
}

uint32_t
Switch::functionalWrite(Packet *pkt)
{
    // Access the buffers in the switch for performing a functional write
    uint32_t num_functional_writes = 0;
    for (unsigned int i = 0; i < m_port_buffers.size(); ++i) {
        num_functional_writes += m_port_buffers[i]->functionalWrite(pkt);
    }
    return num_functional_writes;
}

Switch::
SwitchStats::SwitchStats(Stats::Group *parent)
    : Stats::Group(parent),
      m_avg_utilization(this, "percent_links_utilized")
{

}