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/*
* Copyright (c) 2012-2013 ARM Limited
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*
* The license below extends only to copyright in the software and shall
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* to a hardware implementation of the functionality of the software
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* modified or unmodified, in source code or in binary form.
*
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* this software without specific prior written permission.
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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/// @file
/// Utility functions and datatypes used by AArch64 NEON memory instructions.
#ifndef __ARCH_ARM_INSTS_NEON64_MEM_HH__
#define __ARCH_ARM_INSTS_NEON64_MEM_HH__
#include <cassert>
#include <cstdint>
namespace gem5
{
namespace ArmISA
{
typedef uint64_t XReg;
/// 128-bit NEON vector register.
struct VReg
{
XReg hi;
XReg lo;
};
/// Write a single NEON vector element leaving the others untouched.
inline void
writeVecElem(VReg *dest, XReg src, int index, int eSize)
{
// eSize must be less than 4:
// 0 -> 8-bit elems,
// 1 -> 16-bit elems,
// 2 -> 32-bit elems,
// 3 -> 64-bit elems
assert(eSize <= 3);
int eBits = 8 << eSize;
int lsbPos = index * eBits;
assert(lsbPos < 128);
int shiftAmt = lsbPos % 64;
XReg maskBits = -1;
if (eBits == 64) {
maskBits = 0;
} else {
maskBits = maskBits << eBits;
}
maskBits = ~maskBits;
XReg sMask = maskBits;
maskBits = sMask << shiftAmt;
if (lsbPos < 64) {
dest->lo = (dest->lo & (~maskBits)) | ((src & sMask) << shiftAmt);
} else {
dest->hi = (dest->hi & (~maskBits)) | ((src & sMask) << shiftAmt);
}
}
/// Read a single NEON vector element.
inline XReg
readVecElem(VReg src, int index, int eSize)
{
// eSize must be less than 4:
// 0 -> 8-bit elems,
// 1 -> 16-bit elems,
// 2 -> 32-bit elems,
// 3 -> 64-bit elems
assert(eSize <= 3);
XReg data;
int eBits = 8 << eSize;
int lsbPos = index * eBits;
assert(lsbPos < 128);
int shiftAmt = lsbPos % 64;
XReg maskBits = -1;
if (eBits == 64) {
maskBits = 0;
} else {
maskBits = maskBits << eBits;
}
maskBits = ~maskBits;
if (lsbPos < 64) {
data = (src.lo >> shiftAmt) & maskBits;
} else {
data = (src.hi >> shiftAmt) & maskBits;
}
return data;
}
} // namespace ArmISA
} // namespace gem5
#endif // __ARCH_ARM_INSTS_NEON64_MEM_HH__