src/arch/x86/isa/includes.isa

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////////////////////////////////////////////////////////////////////
//
// Output include file directives. Also import the python modules we
// need for all the x86 custom decoder stuff
//

let {{
    import copy
}};

output header {{
#include <array>
#include <cstring>
#include <iostream>
#include <sstream>

#include "arch/generic/debugfaults.hh"
#include "arch/x86/emulenv.hh"
#include "arch/x86/insts/macroop.hh"
#include "arch/x86/insts/microdebug.hh"
#include "arch/x86/insts/microfpop.hh"
#include "arch/x86/insts/microldstop.hh"
#include "arch/x86/insts/micromediaop.hh"
#include "arch/x86/insts/microregop.hh"
#include "arch/x86/insts/microspecop.hh"
#include "arch/x86/insts/static_inst.hh"
#include "arch/x86/types.hh"
#include "arch/x86/utility.hh"
#include "base/logging.hh"
#include "cpu/static_inst.hh"
#include "mem/packet.hh"
#include "sim/faults.hh"

namespace gem5::X86ISAInst
{
using namespace X86ISA;
} // namespace gem5::X86ISAInst
}};

output decoder {{
#include <algorithm>

#include "arch/x86/decoder.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/microcode_rom.hh"
#include "arch/x86/regs/float.hh"
#include "arch/x86/regs/int.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/regs/segment.hh"
#include "arch/x86/tlb.hh"
#include "base/cprintf.hh"
#include "base/loader/symtab.hh"
#include "base/logging.hh"
#include "cpu/thread_context.hh"  // for Jump::branchTarget()
#include "mem/packet.hh"
#include "sim/full_system.hh"

namespace gem5::X86ISAInst
{
using namespace X86ISA;
} // namespace gem5::X86ISAInst
}};

output exec {{
#include <cmath>
#include <limits>
#include <tuple>

#include "arch/generic/debugfaults.hh"
#include "arch/x86/cpuid.hh"
#include "arch/x86/faults.hh"
#include "arch/x86/memhelpers.hh"
#include "arch/x86/pseudo_inst_abi.hh"
#include "arch/x86/regs/misc.hh"
#include "arch/x86/tlb.hh"
#include "base/compiler.hh"
#include "base/condcodes.hh"
#include "base/logging.hh"
#include "cpu/base.hh"
#include "cpu/exetrace.hh"
#include "debug/X86.hh"
#include "mem/packet.hh"
#include "mem/packet_access.hh"
#include "mem/request.hh"
#include "sim/pseudo_inst.hh"
#include "sim/sim_exit.hh"

namespace gem5::X86ISAInst
{
using namespace X86ISA;
} // namespace gem5::X86ISAInst
}};