/*
 * Copyright (c) 2020 The Regents of the University of California.
 * All rights reserved.
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 * property including but not limited to intellectual property relating
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 * licensed hereunder.  You may use the software subject to the license
 * terms below provided that you ensure that this notice is replicated
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 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
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 * neither the name of the copyright holders nor the names of its
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 * this software without specific prior written permission.
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#include "arch/x86/regs/int.hh"
#include "sim/guest_abi.hh"

namespace gem5
{

struct X86PseudoInstABI
{
    using State = int;
};

GEM5_DEPRECATED_NAMESPACE(GuestABI, guest_abi);
namespace guest_abi
{

template <typename T>
struct Result<X86PseudoInstABI, T>
{
    static void
    store(ThreadContext *tc, const T &ret)
    {
        // This assumes that all pseudo ops have their return value set
        // by the pseudo op instruction. This may need to be revisited if we
        // modify the pseudo op ABI in util/m5/m5op_x86.S
        tc->setIntReg(X86ISA::INTREG_RAX, ret);
    }
};

template <>
struct Argument<X86PseudoInstABI, uint64_t>
{
    static uint64_t
    get(ThreadContext *tc, X86PseudoInstABI::State &state)
    {
        // The first 6 integer arguments are passed in registers, the rest
        // are passed on the stack.

        panic_if(state >= 6, "Too many psuedo inst arguments.");

        using namespace X86ISA;

        const int int_reg_map[] = {
            INTREG_RDI, INTREG_RSI, INTREG_RDX,
            INTREG_RCX, INTREG_R8, INTREG_R9
        };

        return tc->readIntReg(int_reg_map[state++]);
    }
};

} // namespace guest_abi
} // namespace gem5