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/*
* Copyright (c) 2012-2013, 2016-2017 ARM Limited
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*
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#include "cpu/testers/traffic_gen/linear_gen.hh"
#include <algorithm>
#include "base/random.hh"
#include "base/trace.hh"
#include "debug/TrafficGen.hh"
namespace gem5
{
void
LinearGen::enter()
{
// reset the address and the data counter
nextAddr = startAddr;
dataManipulated = 0;
}
PacketPtr
LinearGen::getNextPacket()
{
// choose if we generate a read or a write here
bool isRead = readPercent != 0 &&
(readPercent == 100 || random_mt.random(0, 100) < readPercent);
assert((readPercent == 0 && !isRead) || (readPercent == 100 && isRead) ||
readPercent != 100);
DPRINTF(TrafficGen, "LinearGen::getNextPacket: %c to addr %x, size %d\n",
isRead ? 'r' : 'w', nextAddr, blocksize);
// Add the amount of data manipulated to the total
dataManipulated += blocksize;
PacketPtr pkt = getPacket(nextAddr, blocksize,
isRead ? MemCmd::ReadReq : MemCmd::WriteReq);
// increment the address
nextAddr += blocksize;
// If we have reached the end of the address space, reset the
// address to the start of the range
if (nextAddr > endAddr) {
DPRINTF(TrafficGen, "Wrapping address to the start of "
"the range\n");
nextAddr = startAddr;
}
return pkt;
}
Tick
LinearGen::nextPacketTick(bool elastic, Tick delay) const
{
// Check to see if we have reached the data limit. If dataLimit is
// zero we do not have a data limit and therefore we will keep
// generating requests for the entire residency in this state.
if (dataLimit && dataManipulated >= dataLimit) {
DPRINTF(TrafficGen, "Data limit for LinearGen reached.\n");
// there are no more requests, therefore return MaxTick
return MaxTick;
} else {
// return the time when the next request should take place
Tick wait = random_mt.random(minPeriod, maxPeriod);
// compensate for the delay experienced to not be elastic, by
// default the value we generate is from the time we are
// asked, so the elasticity happens automatically
if (!elastic) {
if (wait < delay)
wait = 0;
else
wait -= delay;
}
return curTick() + wait;
}
}
} // namespace gem5