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from m5.params import *
from m5.objects.PciDevice import PciDevice
from m5.objects.PciDevice import PciMemBar, PciMemUpperBar, PciLegacyIoBar

# PCI device model for an AMD Vega 10 based GPU. The PCI codes and BARs
# correspond to a Vega Frontier Edition hardware device. None of the PCI
# related values in this class should be changed.
#
# This class requires a ROM binary and an MMIO trace to initialize the
# device registers and memory. It is intended only to be used in full-system
# simulation under Linux where the amdgpu driver is modprobed.
class AMDGPUDevice(PciDevice):
    type = 'AMDGPUDevice'
    cxx_header = "dev/amdgpu/amdgpu_device.hh"
    cxx_class = 'gem5::AMDGPUDevice'

    # IDs for AMD Vega 10
    VendorID = 0x1002
    DeviceID = 0x6863
    # Command 0x3 never gets sent indicating IO and Mem bars are enabled. Hard
    # code the command here and deal unassigned BARs on C++ side.
    Command = 0x3
    Status = 0x0280
    Revision = 0x0
    ClassCode = 0x03
    SubClassCode = 0x00
    ProgIF = 0x00

    # Use max possible BAR size for Vega 10. We can override with driver param
    BAR0 = PciMemBar(size='16GiB')
    BAR1 = PciMemUpperBar()
    BAR2 = PciMemBar(size='2MiB')
    BAR3 = PciMemUpperBar()
    BAR4 = PciLegacyIoBar(addr=0xf000, size='256B')
    BAR5 = PciMemBar(size='512KiB')

    InterruptLine = 14
    InterruptPin = 2
    ExpansionROM = 0

    rom_binary = Param.String("ROM binary dumped from hardware")
    trace_file = Param.String("MMIO trace collected on hardware")
    checkpoint_before_mmios = Param.Bool(False, "Take a checkpoint before the"
                                                " device begins sending MMIOs")