| /* |
| * Copyright (c) 2019 ARM Limited |
| * All rights reserved |
| * |
| * The license below extends only to copyright in the software and shall |
| * not be construed as granting a license to any other intellectual |
| * property including but not limited to intellectual property relating |
| * to a hardware implementation of the functionality of the software |
| * licensed hereunder. You may use the software subject to the license |
| * terms below provided that you ensure that this notice is replicated |
| * unmodified and in its entirety in all distributions of the software, |
| * modified or unmodified, in source code or in binary form. |
| * |
| * Copyright (c) 1999-2005 Mark D. Hill and David A. Wood |
| * All rights reserved. |
| * |
| * Redistribution and use in source and binary forms, with or without |
| * modification, are permitted provided that the following conditions are |
| * met: redistributions of source code must retain the above copyright |
| * notice, this list of conditions and the following disclaimer; |
| * redistributions in binary form must reproduce the above copyright |
| * notice, this list of conditions and the following disclaimer in the |
| * documentation and/or other materials provided with the distribution; |
| * neither the name of the copyright holders nor the names of its |
| * contributors may be used to endorse or promote products derived from |
| * this software without specific prior written permission. |
| * |
| * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS |
| * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
| * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
| * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT |
| * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
| * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT |
| * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, |
| * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY |
| * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
| * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| */ |
| |
| /* |
| * $Id$ |
| * |
| */ |
| |
| // CoherenceRequestType |
| enumeration(CoherenceRequestType, desc="...") { |
| GETX, desc="Get eXclusive"; |
| GETS, desc="Get Shared"; |
| PUTX, desc="Put eXclusive"; |
| PUTO, desc="Put Owned"; |
| PUTO_SHARERS, desc="Put Owned, but sharers exist so don't remove from sharers list"; |
| PUTS, desc="Put Shared"; |
| INV, desc="Invalidation"; |
| WRITEBACK_CLEAN_DATA, desc="Clean writeback (contains data)"; |
| WRITEBACK_CLEAN_ACK, desc="Clean writeback (contains no data)"; |
| WRITEBACK_DIRTY_DATA, desc="Dirty writeback (contains data)"; |
| DMA_READ, desc="DMA Read"; |
| DMA_WRITE, desc="DMA Write"; |
| } |
| |
| // CoherenceResponseType |
| enumeration(CoherenceResponseType, desc="...") { |
| ACK, desc="ACKnowledgment, responder doesn't have a copy"; |
| DATA, desc="Data"; |
| DATA_EXCLUSIVE, desc="Data, no processor has a copy"; |
| UNBLOCK, desc="Unblock"; |
| UNBLOCK_EXCLUSIVE, desc="Unblock, we're in E/M"; |
| WB_ACK, desc="Writeback ack"; |
| WB_ACK_DATA, desc="Writeback ack"; |
| WB_NACK, desc="Writeback neg. ack"; |
| DMA_ACK, desc="Ack that a DMA write completed"; |
| } |
| |
| // TriggerType |
| enumeration(TriggerType, desc="...") { |
| ALL_ACKS, desc="See corresponding event"; |
| } |
| |
| // TriggerMsg |
| structure(TriggerMsg, desc="...", interface="Message") { |
| Addr addr, desc="Physical address for this request"; |
| TriggerType Type, desc="Type of trigger"; |
| |
| bool functionalRead(Packet *pkt) { |
| // Trigger message does not hold data |
| return false; |
| } |
| |
| bool functionalWrite(Packet *pkt) { |
| // Trigger message does not hold data |
| return false; |
| } |
| } |
| |
| // RequestMsg (and also forwarded requests) |
| structure(RequestMsg, desc="...", interface="Message") { |
| Addr addr, desc="Physical address for this request"; |
| int Len, desc="Length of Request"; |
| CoherenceRequestType Type, desc="Type of request (GetS, GetX, PutX, etc)"; |
| MachineID Requestor, desc="Node who initiated the request"; |
| MachineType RequestorMachine, desc="type of component"; |
| NetDest Destination, desc="Multicast destination mask"; |
| DataBlock DataBlk, desc="data for the cache line (DMA WRITE request)"; |
| int Acks, desc="How many acks to expect"; |
| MessageSizeType MessageSize, desc="size category of the message"; |
| RubyAccessMode AccessMode, desc="user/supervisor access type"; |
| PrefetchBit Prefetch, desc="Is this a prefetch request"; |
| |
| bool functionalRead(Packet *pkt) { |
| // Read only those messages that contain the data |
| if (Type == CoherenceRequestType:WRITEBACK_CLEAN_DATA || |
| Type == CoherenceRequestType:WRITEBACK_DIRTY_DATA) { |
| return testAndRead(addr, DataBlk, pkt); |
| } |
| return false; |
| } |
| |
| bool functionalWrite(Packet *pkt) { |
| // No check required since all messages are written |
| return testAndWrite(addr, DataBlk, pkt); |
| } |
| } |
| |
| // ResponseMsg (and also unblock requests) |
| structure(ResponseMsg, desc="...", interface="Message") { |
| Addr addr, desc="Physical address for this request"; |
| CoherenceResponseType Type, desc="Type of response (Ack, Data, etc)"; |
| MachineID Sender, desc="Node who sent the data"; |
| MachineType SenderMachine, desc="type of component sending msg"; |
| NetDest Destination, desc="Node to whom the data is sent"; |
| DataBlock DataBlk, desc="data for the cache line"; |
| bool Dirty, desc="Is the data dirty (different than memory)?"; |
| int Acks, desc="How many acks to expect"; |
| MessageSizeType MessageSize, desc="size category of the message"; |
| |
| bool functionalRead(Packet *pkt) { |
| // Read only those messages that contain the data |
| if (Type == CoherenceResponseType:DATA || |
| Type == CoherenceResponseType:DATA_EXCLUSIVE) { |
| return testAndRead(addr, DataBlk, pkt); |
| } |
| return false; |
| } |
| |
| bool functionalWrite(Packet *pkt) { |
| // No check required since all messages are written |
| return testAndWrite(addr, DataBlk, pkt); |
| } |
| } |