/*
 * Copyright (c) 2011-2014 ARM Limited
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 * property including but not limited to intellectual property relating
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 * licensed hereunder.  You may use the software subject to the license
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 * modified or unmodified, in source code or in binary form.
 *
 * Redistribution and use in source and binary forms, with or without
 * modification, are permitted provided that the following conditions are
 * met: redistributions of source code must retain the above copyright
 * notice, this list of conditions and the following disclaimer;
 * redistributions in binary form must reproduce the above copyright
 * notice, this list of conditions and the following disclaimer in the
 * documentation and/or other materials provided with the distribution;
 * neither the name of the copyright holders nor the names of its
 * contributors may be used to endorse or promote products derived from
 * this software without specific prior written permission.
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 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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 */

/**
 * @file
 *
 * The stats for MinorCPU separated from the CPU definition.
 */

#ifndef __CPU_MINOR_STATS_HH__
#define __CPU_MINOR_STATS_HH__

#include "base/statistics.hh"
#include "cpu/base.hh"
#include "sim/ticked_object.hh"

namespace Minor
{

/** Currently unused stats class. */
struct MinorStats : public Stats::Group
{
    MinorStats(BaseCPU *parent);

    /** Number of simulated instructions */
    Stats::Scalar numInsts;

    /** Number of simulated insts and microops */
    Stats::Scalar numOps;

    /** Number of ops discarded before committing */
    Stats::Scalar numDiscardedOps;

    /** Number of times fetch was asked to suspend by Execute */
    Stats::Scalar numFetchSuspends;

    /** Number of cycles in quiescent state */
    Stats::Scalar quiesceCycles;

    /** CPI/IPC for total cycle counts and macro insts */
    Stats::Formula cpi;
    Stats::Formula ipc;

    /** Number of instructions by type (OpClass) */
    Stats::Vector2d committedInstType;

};

}

#endif /* __CPU_MINOR_STATS_HH__ */