tree 85bd54efc30f0a1f4e09945ea6d8474a72652e72
parent 631bfb6d257ed849270400cc7f6a39afdb732dff
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1553623331 +0000
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1553765661 +0000

arch-arm: Fix index generation for VecElem operands

Current operand generation is not providing VecElems with the right
vector index and element index.
The bug was covered when registers were 128 bit wide, but with SVE we
have augmented the vector register size and the bug has been exposed.

E.g. With dest = 2,

FpDestP2 = (vec_index = 0, elem_index = 4)

whereas it should be

FpDestP2 = (vec_index = 1, elem_index = 0)

Change-Id: Iad02fb477afd0d3dd3d437bf2ca4338fbd142107
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Ciro Santilli <ciro.santilli@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/17710