tree 250d1ff3f81908377d8a2c00a33ef358a27f9717
parent e2e25f8139f6c30187cf86c5978f71bf9f32593b
author Tony Gutierrez <anthony.gutierrez@amd.com> 1524872310 -0400
committer Anthony Gutierrez <anthony.gutierrez@amd.com> 1588262078 +0000

arch-gcn3: Add files for arch gcn3 (GPU machine ISA)

Decoder: gpu_decoder.hh and decoder.cc:
    The decoder is defined in these files. The decoder
    is implemented as a lookup table of function pointers
    where each decode function will decode to a unique
    ISA instruction, or do some sub-decoding to infer
    the next decode function to call.

    The format for each OP encoding is defined in the
    header file.

Registers:
    registers.[hh|cc] define the special registers and
    operand selector values, which are used to map
    operands to registers/special values. many
    convenience functions are also provides to determine
    the source/type of an operand, for example vector
    vs. scalar, register operand vs. constant, etc.

GPU ISA:
    Some special GPU ISA state is maintained in gpu_isa.hh
    and isa.cc. This class is used to hold some special
    registers and values that can be used as operands
    by ISA instructions. Eventually more ISA-specific
    state should be moved here, and out of the WF class.

Vector Operands:
    The operands for GCN3 instructions are defined in
    operand.hh. This file defines both scalar and
    vector operands wth GCN3 specific semantics. The
    vector operand class is desgned around the generic
    vec_reg.hh that is already present in gem5.

Instructions:
    The GCN3 instructions are defined and implemented
    throughout gpu_static_inst.[hh|cc], instructions.[hh|cc],
    op_encodings.[hh|cc], and inst_util.hh. GCN3 instructions
    all fall under one of the OP encoding types; for example
    scalar memory operands are of the type SMEM, vector
    ALU instructions can be VOP3, VOP2, etc. The base code
    common to all instructions of a certain OP encoding type
    is implemented in the OP encodings files, which includes
    operand information, disassembly methods, encoding type,
    etc.

    Each individual ISA isntruction is implemented as
    a class object in instructions.[hh|cc] and are derived
    from one of the OP encoding types. The instructions.cc
    file is primarily for the execute() methods of each
    individual instruction, and the header file provides
    the class definition and a few instruction specific
    API calls.

    Note that these instruction classes were auto-generated
    but not using the gem5 ISA description language. A
    custom ISA description was used and that cannot be released
    publicly, therefore we are providing them already in C++.

Change-Id: I14d2a02d6b87109f41341c8f50a69a2cca9f3d14
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28127
Reviewed-by: Matt Sinclair <mattdsinclair@gmail.com>
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Anthony Gutierrez <anthony.gutierrez@amd.com>
Tested-by: kokoro <noreply+kokoro@google.com>