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# Copyright (c) 2008 The Regents of The University of Michigan
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#
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from m5.SimObject import SimObject
from m5.params import *
from m5.proxy import *
from m5.objects.PciDevice import PciDevice, PciMemBar
class CopyEngine(PciDevice):
type = 'CopyEngine'
cxx_header = "dev/pci/copy_engine.hh"
cxx_class = 'gem5::CopyEngine'
dma = VectorRequestPort("Copy engine DMA port")
VendorID = 0x8086
DeviceID = 0x1a38
Revision = 0xA2 # CM2 stepping (newest listed)
SubsystemID = 0
SubsystemVendorID = 0
Status = 0x0000
SubClassCode = 0x08
ClassCode = 0x80
ProgIF = 0x00
MaximumLatency = 0x00
MinimumGrant = 0xff
InterruptLine = 0x20
InterruptPin = 0x01
BAR0 = PciMemBar(size='1KiB')
ChanCnt = Param.UInt8(4, "Number of DMA channels that exist on device")
XferCap = Param.MemorySize('4KiB',
"Number of bits of transfer size that are supported")
latBeforeBegin = Param.Latency('20ns',
"Latency after a DMA command is seen before it's proccessed")
latAfterCompletion = Param.Latency('20ns',
"Latency after a DMA command is complete before "
"it's reported as such")