tree 28a3af6326358950beb7bad91000401f3030892d
parent 4db981576e5f50f7b21667362b2f5bdb530fb06d
author Giacomo Travaglini <giacomo.travaglini@arm.com> 1664459816 +0100
committer Giacomo Travaglini <giacomo.travaglini@arm.com> 1666866818 +0000

dev-arm: Implement System Security Control registers

This block of system registers is part of the N1 SDP [1]

[1]: https://developer.arm.com/documentation/101489/0000/\
    Programmers-model/System-Security-Control-registers

Change-Id: I2ecf5cd247bd68eddcd359e91f3954070dbffaa8
Signed-off-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Reviewed-by: Richard Cooper <richard.cooper@arm.com>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/64951
Maintainer: Andreas Sandberg <andreas.sandberg@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
Reviewed-by: Andreas Sandberg <andreas.sandberg@arm.com>