| commit | 9cd61d000a33a91f679d4c47f45b89c4b68592d4 | [log] [tgz] |
|---|---|---|
| author | Roger Chang <rogerycchang@google.com> | Fri Dec 23 10:05:46 2022 +0800 |
| committer | Roger Chang <rogerycchang@google.com> | Fri Dec 23 23:01:16 2022 +0000 |
| tree | 8db2ee87e770de0f03f5e70998e804d27abf5dfd | |
| parent | 9ce8c9b81c046328ced0c3b9e41789c593b4bf94 [diff] |
arch-riscv: Correct the IllegalInstFault messege of instruction c.addi4spn In Riscv Manual Volumn I: Unpriviledged ISA section 18.5, c.addi4spn will not working if imm == 0, not machInst == 0. It is changed in the https://gem5-review.git.corp.google.com/c/public/gem5/+/66732, and here is the additional patch to the CL. Change-Id: I2a3c9660dc43f1399f68e03c4f59207f869807a0 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/66931 Reviewed-by: Yu-hsin Wang <yuhsingw@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com> Tested-by: kokoro <noreply+kokoro@google.com>