arch-arm: move serialize and unserialize definition to cpp file
Change-Id: I9ac64184d3fe36617f474a714b228b55b9a90976
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/36115
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>
diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 217f432..9b1cde3 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -2351,6 +2351,22 @@
}
void
+ISA::serialize(CheckpointOut &cp) const
+{
+ DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
+ SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+}
+
+void
+ISA::unserialize(CheckpointIn &cp)
+{
+ DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
+ UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
+ CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
+ updateRegMap(tmp_cpsr);
+}
+
+void
ISA::addressTranslation64(TLB::ArmTranslationType tran_type,
BaseTLB::Mode mode, Request::Flags flags, RegVal val)
{
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 4a824ed..6b9dd3c 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -810,21 +810,8 @@
static void zeroSveVecRegUpperPart(VecRegContainer &vc,
unsigned eCount);
- void
- serialize(CheckpointOut &cp) const override
- {
- DPRINTF(Checkpoint, "Serializing Arm Misc Registers\n");
- SERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
- }
-
- void
- unserialize(CheckpointIn &cp) override
- {
- DPRINTF(Checkpoint, "Unserializing Arm Misc Registers\n");
- UNSERIALIZE_ARRAY(miscRegs, NUM_PHYS_MISCREGS);
- CPSR tmp_cpsr = miscRegs[MISCREG_CPSR];
- updateRegMap(tmp_cpsr);
- }
+ void serialize(CheckpointOut &cp) const override;
+ void unserialize(CheckpointIn &cp) override;
void startup() override;