src/arch/arm/fastmodel/CortexA76/cortex_a76.hh

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#ifndef __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__
#define __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__

#include "arch/arm/fastmodel/CortexA76/thread_context.hh"
#include "arch/arm/fastmodel/amba_ports.hh"
#include "arch/arm/fastmodel/iris/cpu.hh"
#include "params/FastModelCortexA76.hh"
#include "params/FastModelCortexA76Cluster.hh"
#include "scx/scx.h"
#include "sim/port.hh"
#include "systemc/ext/core/sc_module.hh"

namespace gem5
{

class BaseCPU;

GEM5_DEPRECATED_NAMESPACE(FastModel, fastmodel);
namespace fastmodel
{

// The fast model exports a class called scx_evs_CortexA76x1 which represents
// the subsystem described in LISA+. This class specializes it to export gem5
// ports and interface with its peer gem5 CPU. The gem5 CPU inherits from the
// gem5 BaseCPU class and implements its API, while this class actually does
// the work.
class CortexA76Cluster;

class CortexA76 : public Iris::CPU<CortexA76TC>
{
  protected:
    typedef Iris::CPU<CortexA76TC> Base;

    CortexA76Cluster *cluster = nullptr;
    int num = 0;

  public:
    PARAMS(FastModelCortexA76);
    CortexA76(const Params &p) :
        Base(p, scx::scx_get_iris_connection_interface())
    {}

    void initState() override;

    template <class T>
    void set_evs_param(const std::string &n, T val);

    void setCluster(CortexA76Cluster *_cluster, int _num);

    Port &getPort(const std::string &if_name,
            PortID idx=InvalidPortID) override;
};

class CortexA76Cluster : public SimObject
{
  private:
    std::vector<CortexA76 *> cores;
    sc_core::sc_module *evs;

  public:
    PARAMS(FastModelCortexA76Cluster);
    template <class T>
    void
    set_evs_param(const std::string &n, T val)
    {
        scx::scx_set_parameter(evs->name() + std::string(".") + n, val);
    }

    CortexA76 *getCore(int num) const { return cores.at(num); }
    sc_core::sc_module *getEvs() const { return evs; }

    CortexA76Cluster(const Params &p);

    Port &getPort(const std::string &if_name,
            PortID idx=InvalidPortID) override;
};

template <class T>
inline void
CortexA76::set_evs_param(const std::string &n, T val)
{
    for (auto &path: params().thread_paths)
        cluster->set_evs_param(path + "." + n, val);
}

} // namespace fastmodel
} // namespace gem5

#endif // __ARCH_ARM_FASTMODEL_CORTEXA76_CORETEX_A76_HH__