commit a21573cef0ead79035f682c776c41d460611c689
author Adrian Herrera <adrian.herrera@arm.com> Tue Sep 29 10:31:49 2020 +0100
committer Adrian Herrera <adrian.herrera@arm.com> Tue Sep 29 18:38:48 2020 +0000
tree 9ced2fe0aa5e30fa2d26e7458d97d25094bed3a8
parent 87baeab20fdba0fc5a29b9db744bc377858e3228

dev-arm: SMMUv3, default CMDQ entries to 128

From Linux 587e6c10a7ce89a5924fdbeff2ec524fbd6a124b, SMMUv3
implementations in 64-bit platforms must report a minimum of 128 CMDQ
entries via SMMU_IDR1. Otherwise, the SMMUv3 Linux driver returns -ENXIO.

Change-Id: I304aac1b734515b3077003e8d67cc19730afc67f
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/35297
Reviewed-by: Giacomo Travaglini <giacomo.travaglini@arm.com>
Maintainer: Giacomo Travaglini <giacomo.travaglini@arm.com>
Tested-by: kokoro <noreply+kokoro@google.com>

src/dev/arm/SMMUv3.py

diff --git a/src/dev/arm/SMMUv3.py b/src/dev/arm/SMMUv3.py
index 29c1568..f53b8ec 100644
--- a/src/dev/arm/SMMUv3.py
+++ b/src/dev/arm/SMMUv3.py
@@ -162,9 +162,9 @@
     # [0] S2P = 0b1, Stage 2 translation supported.
     smmu_idr0 = Param.UInt32(0x094C100F, "SMMU_IDR0 register");
 
-    # [25:21] CMDQS = 0b00101, Maximum number of Command queue entries
-    # as log 2 (entries) (0b00101 = 32 entries).
-    smmu_idr1 = Param.UInt32(0x00A00000, "SMMU_IDR1 register");
+    # [25:21] CMDQS = 0b00111, Maximum number of Command queue entries
+    # as log 2 (entries) (0b00111 = 128 entries).
+    smmu_idr1 = Param.UInt32(0x00E00000, "SMMU_IDR1 register");
 
     smmu_idr2 = Param.UInt32(0, "SMMU_IDR2 register");
     smmu_idr3 = Param.UInt32(0, "SMMU_IDR3 register");