arch-riscv: Add VS field to the STATUS CSR
Per RISC-V ISA Manual, vol II, section 3.1.6, page 20, the VS field
is located at bits 10..9 of mstatus. Per section 4.1.1, page 63,
the VS field is located at the same bits of sstatus.
Change-Id: Ifda44441c551a23ed892fb8ac7ef31fa98f0b6db
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65274
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>
1 file changed
