tree 7c82711c9c2de5ef57b83dd6a3fdfbe5b252e04a
parent 26c27b1bf8c7aac351f90db9f0dccc775b6d8caa
author Hoa Nguyen <hoanguyen@ucdavis.edu> 1667521816 -0700
committer Hoa Nguyen <hoanguyen@ucdavis.edu> 1667595749 +0000

arch-riscv: Add VS field to the STATUS CSR

Per RISC-V ISA Manual, vol II, section 3.1.6, page 20, the VS field
is located at bits 10..9 of mstatus. Per section 4.1.1, page 63,
the VS field is located at the same bits of sstatus.

Change-Id: Ifda44441c551a23ed892fb8ac7ef31fa98f0b6db
Signed-off-by: Hoa Nguyen <hoanguyen@ucdavis.edu>
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/65274
Reviewed-by: Jason Lowe-Power <power.jg@gmail.com>
Maintainer: Jason Lowe-Power <power.jg@gmail.com>
Tested-by: kokoro <noreply+kokoro@google.com>