| commit | aaf294af5c8e027ba68ddb41198d6f09aee4aeed | [log] [tgz] |
|---|---|---|
| author | Nils Asmussen <nils.asmussen@barkhauseninstitut.org> | Mon Feb 24 13:47:43 2020 +0100 |
| committer | Nils Asmussen <nils.asmussen@barkhauseninstitut.org> | Wed Apr 29 11:41:55 2020 +0000 |
| tree | 011066ca6599687de90d249e54b448007fbfc7bd | |
| parent | 54d769308d0ccc5a70db8caa5bb494d2d7d08bd9 [diff] |
arch-riscv: ignore writes to SXL/UXL fields in status register. We currently only support SXL=UXL=2 (64 bit). These fields are WARL, so that we have to make sure that no other value can be set. Change-Id: I62ddc7d68b8c31ca655ba1ccee7a294912f46b09 Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/25651 Tested-by: kokoro <noreply+kokoro@google.com> Reviewed-by: Jason Lowe-Power <power.jg@gmail.com> Maintainer: Jason Lowe-Power <power.jg@gmail.com>