diff --git a/src/arch/arm/semihosting.cc b/src/arch/arm/semihosting.cc
index 3f9c095..2b769ef 100644
--- a/src/arch/arm/semihosting.cc
+++ b/src/arch/arm/semihosting.cc
@@ -47,7 +47,7 @@
 #include "debug/Semihosting.hh"
 #include "dev/serial/serial.hh"
 #include "mem/physical.hh"
-#include "mem/port_proxy.hh"
+#include "mem/secure_port_proxy.hh"
 #include "params/ArmSemihosting.hh"
 #include "sim/byteswap.hh"
 #include "sim/sim_exit.hh"
diff --git a/src/mem/SConscript b/src/mem/SConscript
index b9d5672..95d8654 100644
--- a/src/mem/SConscript
+++ b/src/mem/SConscript
@@ -74,6 +74,7 @@
 Source('packet_queue.cc')
 Source('port_proxy.cc')
 Source('physical.cc')
+Source('secure_port_proxy.cc')
 Source('simple_mem.cc')
 Source('snoop_filter.cc')
 Source('stack_dist_calc.cc')
diff --git a/src/mem/port_proxy.cc b/src/mem/port_proxy.cc
index a36e66a..f13bcbe 100644
--- a/src/mem/port_proxy.cc
+++ b/src/mem/port_proxy.cc
@@ -87,22 +87,3 @@
 
     delete [] buf;
 }
-
-
-void
-SecurePortProxy::readBlob(Addr addr, uint8_t *p, int size) const
-{
-    readBlobPhys(addr, Request::SECURE, p, size);
-}
-
-void
-SecurePortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
-{
-    writeBlobPhys(addr, Request::SECURE, p, size);
-}
-
-void
-SecurePortProxy::memsetBlob(Addr addr, uint8_t v, int size) const
-{
-    memsetBlobPhys(addr, Request::SECURE, v, size);
-}
diff --git a/src/mem/port_proxy.hh b/src/mem/port_proxy.hh
index e48942e..bed448d 100644
--- a/src/mem/port_proxy.hh
+++ b/src/mem/port_proxy.hh
@@ -165,23 +165,6 @@
 };
 
 
-/**
- * This object is a proxy for a structural port, to be used for debug
- * accesses to secure memory.
- *
- * The addresses are interpreted as physical addresses to secure memory.
- */
-class SecurePortProxy : public PortProxy
-{
-  public:
-    SecurePortProxy(MasterPort &port, unsigned int cache_line_size)
-        : PortProxy(port, cache_line_size) {}
-
-    void readBlob(Addr addr, uint8_t *p, int size) const override;
-    void writeBlob(Addr addr, const uint8_t *p, int size) const override;
-    void memsetBlob(Addr addr, uint8_t val, int size) const override;
-};
-
 template <typename T>
 T
 PortProxy::read(Addr address) const
diff --git a/src/mem/secure_port_proxy.cc b/src/mem/secure_port_proxy.cc
new file mode 100644
index 0000000..7bf23d7
--- /dev/null
+++ b/src/mem/secure_port_proxy.cc
@@ -0,0 +1,58 @@
+/*
+ * Copyright (c) 2012, 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+#include "mem/secure_port_proxy.hh"
+
+void
+SecurePortProxy::readBlob(Addr addr, uint8_t *p, int size) const
+{
+    readBlobPhys(addr, Request::SECURE, p, size);
+}
+
+void
+SecurePortProxy::writeBlob(Addr addr, const uint8_t *p, int size) const
+{
+    writeBlobPhys(addr, Request::SECURE, p, size);
+}
+
+void
+SecurePortProxy::memsetBlob(Addr addr, uint8_t v, int size) const
+{
+    memsetBlobPhys(addr, Request::SECURE, v, size);
+}
diff --git a/src/mem/secure_port_proxy.hh b/src/mem/secure_port_proxy.hh
new file mode 100644
index 0000000..857d70b
--- /dev/null
+++ b/src/mem/secure_port_proxy.hh
@@ -0,0 +1,81 @@
+/*
+ * Copyright (c) 2011-2013, 2018 ARM Limited
+ * All rights reserved
+ *
+ * The license below extends only to copyright in the software and shall
+ * not be construed as granting a license to any other intellectual
+ * property including but not limited to intellectual property relating
+ * to a hardware implementation of the functionality of the software
+ * licensed hereunder.  You may use the software subject to the license
+ * terms below provided that you ensure that this notice is replicated
+ * unmodified and in its entirety in all distributions of the software,
+ * modified or unmodified, in source code or in binary form.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are
+ * met: redistributions of source code must retain the above copyright
+ * notice, this list of conditions and the following disclaimer;
+ * redistributions in binary form must reproduce the above copyright
+ * notice, this list of conditions and the following disclaimer in the
+ * documentation and/or other materials provided with the distribution;
+ * neither the name of the copyright holders nor the names of its
+ * contributors may be used to endorse or promote products derived from
+ * this software without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+ * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+ * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+ * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+ * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+ * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+ * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Authors: Andreas Hansson
+ */
+
+/**
+ * @file
+ * PortProxy Object Declaration.
+ *
+ * Port proxies are used when non-structural entities need access to
+ * the memory system (or structural entities that want to peak into
+ * the memory system without making a real memory access).
+ *
+ * Proxy objects replace the previous FunctionalPort, TranslatingPort
+ * and VirtualPort objects, which provided the same functionality as
+ * the proxies, but were instances of ports not corresponding to real
+ * structural ports of the simulated system. Via the port proxies all
+ * the accesses go through an actual port (either the system port,
+ * e.g. for processes or initialisation, or a the data port of the
+ * CPU, e.g. for threads) and thus are transparent to a potentially
+ * distributed memory and automatically adhere to the memory map of
+ * the system.
+ */
+
+#ifndef __MEM_SECURE_PORT_PROXY_HH__
+#define __MEM_SECURE_PORT_PROXY_HH__
+
+#include "mem/port_proxy.hh"
+
+/**
+ * This object is a proxy for a structural port, to be used for debug
+ * accesses to secure memory.
+ *
+ * The addresses are interpreted as physical addresses to secure memory.
+ */
+class SecurePortProxy : public PortProxy
+{
+  public:
+    SecurePortProxy(MasterPort &port, unsigned int cache_line_size)
+        : PortProxy(port, cache_line_size) {}
+
+    void readBlob(Addr addr, uint8_t *p, int size) const override;
+    void writeBlob(Addr addr, const uint8_t *p, int size) const override;
+    void memsetBlob(Addr addr, uint8_t val, int size) const override;
+};
+
+#endif // __MEM_SECURE_PORT_PROXY_HH__