diff --git a/src/arch/arm/isa.cc b/src/arch/arm/isa.cc
index 8813082..a30fd94 100644
--- a/src/arch/arm/isa.cc
+++ b/src/arch/arm/isa.cc
@@ -79,8 +79,7 @@
 } // anonymous namespace
 
 ISA::ISA(const Params &p) : BaseISA(p), system(NULL),
-    _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop),
-    afterStartup(false)
+    _decoderFlavor(p.decoderFlavor), pmu(p.pmu), impdefAsNop(p.impdef_nop)
 {
     _regClasses.push_back(&flatIntRegClass);
     _regClasses.push_back(&floatRegClass);
@@ -513,8 +512,6 @@
             tc->setHtmCheckpointPtr(std::move(cpt));
         }
     }
-
-    afterStartup = true;
 }
 
 void
diff --git a/src/arch/arm/isa.hh b/src/arch/arm/isa.hh
index 218cf9c..1f7a756 100644
--- a/src/arch/arm/isa.hh
+++ b/src/arch/arm/isa.hh
@@ -104,8 +104,6 @@
          */
         bool impdefAsNop;
 
-        bool afterStartup;
-
         SelfDebug * selfDebug;
 
         const MiscRegLUTEntryInitializer
@@ -394,17 +392,6 @@
 
         enums::DecoderFlavor decoderFlavor() const { return _decoderFlavor; }
 
-        /** Returns true if the ISA has a GICv3 cpu interface */
-        bool
-        haveGICv3CpuIfc() const
-        {
-            // gicv3CpuInterface is initialized at startup time, hence
-            // trying to read its value before the startup stage will lead
-            // to an error
-            assert(afterStartup);
-            return gicv3CpuInterface != nullptr;
-        }
-
         PARAMS(ArmISA);
 
         ISA(const Params &p);
diff --git a/src/arch/arm/regs/misc.cc b/src/arch/arm/regs/misc.cc
index b19c905..142b25f 100644
--- a/src/arch/arm/regs/misc.cc
+++ b/src/arch/arm/regs/misc.cc
@@ -1619,12 +1619,24 @@
 }
 
 Fault
+faultGicv3(const MiscRegLUTEntry &entry,
+    ThreadContext *tc, const MiscRegOp64 &inst)
+{
+    auto gic = static_cast<ArmSystem*>(tc->getSystemPtr())->getGIC();
+    if (!gic->supportsVersion(BaseGic::GicVersion::GIC_V3)) {
+        return inst.undefined();
+    } else {
+        return NoFault;
+    }
+}
+
+Fault
 faultIccSgiEL1(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
 {
-    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-    if (!isa->haveGICv3CpuIfc())
-        return inst.undefined();
+    if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
+        return fault;
+    }
 
     const Gicv3CPUInterface::ICH_HCR_EL2 ich_hcr =
         tc->readMiscReg(MISCREG_ICH_HCR_EL2);
@@ -1643,9 +1655,9 @@
 faultIccSgiEL2(const MiscRegLUTEntry &entry,
     ThreadContext *tc, const MiscRegOp64 &inst)
 {
-    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-    if (!isa->haveGICv3CpuIfc())
-        return inst.undefined();
+    if (auto fault = faultGicv3(entry, tc, inst); fault != NoFault) {
+        return fault;
+    }
 
     const SCR scr = tc->readMiscReg(MISCREG_SCR_EL3);
     if (ArmSystem::haveEL(tc, EL3) && scr.irq && scr.fiq) {
diff --git a/src/arch/arm/utility.cc b/src/arch/arm/utility.cc
index d7185f2..6764569 100644
--- a/src/arch/arm/utility.cc
+++ b/src/arch/arm/utility.cc
@@ -626,19 +626,11 @@
                 break;
               // GICv3 regs
               case MISCREG_ICC_SGI0R:
-                {
-                    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-                    if (isa->haveGICv3CpuIfc())
-                        trap_to_hyp = hcr.fmo;
-                }
+                trap_to_hyp = hcr.fmo;
                 break;
               case MISCREG_ICC_SGI1R:
               case MISCREG_ICC_ASGI1R:
-                {
-                    auto *isa = static_cast<ArmISA::ISA *>(tc->getIsaPtr());
-                    if (isa->haveGICv3CpuIfc())
-                        trap_to_hyp = hcr.imo;
-                }
+                trap_to_hyp = hcr.imo;
                 break;
               case MISCREG_CNTFRQ ... MISCREG_CNTV_TVAL:
                 // CNTFRQ may be trapped only on reads