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from m5.params import *
from m5.proxy import *
from m5.SimObject import SimObject

from m5.objects.ClockedObject import ClockedObject
from m5.objects.Compressors import BaseCacheCompressor
from m5.objects.Prefetcher import BasePrefetcher
from m5.objects.ReplacementPolicies import *
from m5.objects.Tags import *

# Enum for cache clusivity, currently mostly inclusive or mostly
# exclusive.
class Clusivity(Enum):
    vals = ["mostly_incl", "mostly_excl"]


class WriteAllocator(SimObject):
    type = "WriteAllocator"
    cxx_header = "mem/cache/cache.hh"
    cxx_class = "gem5::WriteAllocator"

    # Control the limits for when the cache introduces extra delays to
    # allow whole-line write coalescing, and eventually switches to a
    # write-no-allocate policy.
    coalesce_limit = Param.Unsigned(
        2, "Consecutive lines written before " "delaying for coalescing"
    )
    no_allocate_limit = Param.Unsigned(
        12, "Consecutive lines written before" " skipping allocation"
    )

    delay_threshold = Param.Unsigned(
        8,
        "Number of delay quanta imposed on an "
        "MSHR with write requests to allow for "
        "write coalescing",
    )

    block_size = Param.Int(Parent.cache_line_size, "block size in bytes")


class BaseCache(ClockedObject):
    type = "BaseCache"
    abstract = True
    cxx_header = "mem/cache/base.hh"
    cxx_class = "gem5::BaseCache"

    size = Param.MemorySize("Capacity")
    assoc = Param.Unsigned("Associativity")

    tag_latency = Param.Cycles("Tag lookup latency")
    data_latency = Param.Cycles("Data access latency")
    response_latency = Param.Cycles("Latency for the return path on a miss")

    warmup_percentage = Param.Percent(
        0, "Percentage of tags to be touched to warm up the cache"
    )

    max_miss_count = Param.Counter(
        0, "Number of misses to handle before calling exit"
    )

    mshrs = Param.Unsigned("Number of MSHRs (max outstanding requests)")
    demand_mshr_reserve = Param.Unsigned(1, "MSHRs reserved for demand access")
    tgts_per_mshr = Param.Unsigned("Max number of accesses per MSHR")
    write_buffers = Param.Unsigned(8, "Number of write buffers")

    is_read_only = Param.Bool(False, "Is this cache read only (e.g. inst)")

    prefetcher = Param.BasePrefetcher(NULL, "Prefetcher attached to cache")
    prefetch_on_access = Param.Bool(
        False,
        "Notify the hardware prefetcher on every access (not just misses)",
    )
    prefetch_on_pf_hit = Param.Bool(
        False, "Notify the hardware prefetcher on hit on prefetched lines"
    )

    tags = Param.BaseTags(BaseSetAssoc(), "Tag store")
    replacement_policy = Param.BaseReplacementPolicy(
        LRURP(), "Replacement policy"
    )

    compressor = Param.BaseCacheCompressor(NULL, "Cache compressor.")
    replace_expansions = Param.Bool(
        True,
        "Apply replacement policy to "
        "decide which blocks should be evicted on a data expansion",
    )
    # When a block passes from uncompressed to compressed, it may become
    # co-allocatable with another existing entry of the same superblock,
    # so try move the block to co-allocate it
    move_contractions = Param.Bool(
        True, "Try to co-allocate blocks that " "contract"
    )

    sequential_access = Param.Bool(
        False, "Whether to access tags and data sequentially"
    )

    cpu_side = ResponsePort("Upstream port closer to the CPU and/or device")
    mem_side = RequestPort("Downstream port closer to memory")

    addr_ranges = VectorParam.AddrRange(
        [AllMemory], "Address range for the CPU-side port (to allow striping)"
    )

    system = Param.System(Parent.any, "System we belong to")

    # Determine if this cache sends out writebacks for clean lines, or
    # simply clean evicts. If this cache does not have a downstream cache,
    # the cache should not writeback clean lines not to waste memory
    # bandwidth. If this cache has a downstream cache whose clusivity is
    # mostly exclusive (i.e., victim cache), this shoule be set to True.
    # If not, there will never be any spills from read-only caches (e.g.,
    # L1I cache, MMU cache of ARM) to the downstream cache.
    # In case of the downstream cache is mostly inclusive, this should be
    # set to False.
    writeback_clean = Param.Bool(False, "Writeback clean lines")

    # Control whether this cache should be mostly inclusive or mostly
    # exclusive with respect to upstream caches. The behaviour on a
    # fill is determined accordingly. For a mostly inclusive cache,
    # blocks are allocated on all fill operations. Thus, L1 caches
    # should be set as mostly inclusive even if they have no upstream
    # caches. In the case of a mostly exclusive cache, fills are not
    # allocating unless they came directly from a non-caching source,
    # e.g. a table walker. Additionally, on a hit from an upstream
    # cache a line is dropped for a mostly exclusive cache.
    clusivity = Param.Clusivity("mostly_incl", "Clusivity with upstream cache")

    # The write allocator enables optimizations for streaming write
    # accesses by first coalescing writes and then avoiding allocation
    # in the current cache. Typically, this would be enabled in the
    # data cache.
    write_allocator = Param.WriteAllocator(NULL, "Write allocator")


class Cache(BaseCache):
    type = "Cache"
    cxx_header = "mem/cache/cache.hh"
    cxx_class = "gem5::Cache"


class NoncoherentCache(BaseCache):
    type = "NoncoherentCache"
    cxx_header = "mem/cache/noncoherent_cache.hh"
    cxx_class = "gem5::NoncoherentCache"

    # This is typically a last level cache and any clean
    # writebacks would be unnecessary traffic to the main memory.
    writeback_clean = False