tree 4f53abd4ae4c4f39e1de72e81a0de9a04e28a4cc
parent 7de8ac1b93fded6b5a9c64061dc6130711ad1808
author Timothy Hayes <timothy.hayes@arm.com> 1587461162 +0100
committer Pouya Fotouhi <pfotouhi@ucdavis.edu> 1588387070 +0000

mem-ruby: fix MESI_Three_Level erroneous transition

The MESI_Three_Level protocol includes a transition in its L1
definition to invalidate an SM state but this transition does
not notify the L0 cache. The unintended side effect of this
allows stale values to be read by the L0 cache. This can cause
incorrect behaviour when executing LL/SC based mutexes. This
patch ensures that all invalidates to SM states are exposed to
the L0 cache.

Change-Id: I7fefabdaa8027fdfa4c9c362abd7e467493196aa
Reviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/28047
Reviewed-by: John Alsop <johnathan.alsop@amd.com>
Reviewed-by: Pouya Fotouhi <pfotouhi@ucdavis.edu>
Maintainer: Bobby R. Bruce <bbruce@ucdavis.edu>
Tested-by: kokoro <noreply+kokoro@google.com>