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{
  "commit": "b13b4850951b4507cabee27a8c2a748c93a20daf",
  "tree": "de00ea5ea48a6d900e7dd7ee127910d3085f16e3",
  "parents": [
    "dcc2f4caaf912e5a4125ac5bfab16ad938a32c9d"
  ],
  "author": {
    "name": "Tiago Mück",
    "email": "tiago.muck@arm.com",
    "time": "Mon Jun 22 14:09:50 2020 -0500"
  },
  "committer": {
    "name": "Tiago Mück",
    "email": "tiago.muck@arm.com",
    "time": "Tue Mar 16 15:28:44 2021 +0000"
  },
  "message": "configs,mem-ruby: CHI-based Ruby protocol\n\nThis patch add a new Ruby cache coherence protocol based on Arm\u0027 AMBA5\nCHI specification. The CHI protocol defines and implements two state\nmachine types:\n\n- Cache_Controller: generic cache controller that can be configured as:\n    - Top-level L1 I/D cache\n    - A intermediate level (L2, L3, ...) private or shared cache\n    - A CHI home node (i.e. the point of coherence of the system and\n        has the global directory)\n    - A DMA requester\n\n- Memory_Controller: implements a CHI slave node and interfaces with\n    gem5 memory controller. This controller has the functionality of a\n    Directory_Controller on the other Ruby protocols, except it doesn\u0027t\n    have a directory.\n\nThe Cache_Controller has multiple cache allocation/deallocation\nparameters to control the clusivity with respect to upstream caches.\nAllocation can be completely disabled to use Cache_Controller as a\nDMA requester or as a home node without a shared LLC.\n\nThe standard configuration file configs/ruby/CHI.py provides a\n\u0027create_system\u0027 compatible with configs/example/fs.py and\nconfigs/example/se.py and creates a system with private L1/L2 caches\nper core and a shared LLC at the home nodes. Different cache topologies\ncan be defined by modifying \u0027create_system\u0027 or by creating custom\nscripts using the structures defined in configs/ruby/CHI.py.\n\nThis patch also includes the \u0027CustomMesh\u0027 topology script to be used\nwith CHI. CustomMesh generates a 2D mesh topology with the placement\nof components manually defined in a separate configuration file using\nthe --noc-config parameter.\nThe example in configs/example/noc_config/2x4.yaml creates a simple 2x4\nmesh. For example, to run a SE mode simulation, with 4 cores,\n4 mem ctnrls, and 4 home nodes (L3 caches):\n\nbuild/ARM/gem5.opt configs/example/se.py \\\n--cmd \u0027tests/test-progs/hello/bin/arm/linux/hello\u0027 \\\n--ruby --num-cpus\u003d4 --num-dirs\u003d4 --num-l3caches\u003d4 \\\n--topology\u003dCustomMesh --noc-config\u003dconfigs/example/noc_config/2x4.yaml\n\nIf one doesn\u0027t care about the component placement on the interconnect,\nthe \u0027Crossbar\u0027 and \u0027Pt2Pt\u0027 may be used and they do not require the\n--noc-config option.\n\nAdditional authors:\n    Joshua Randall \u003cjoshua.randall@arm.com\u003e\n    Pedro Benedicte \u003cpedro.benedicteillescas@arm.com\u003e\n    Tuan Ta \u003ctuan.ta2@arm.com\u003e\n\nJIRA: https://gem5.atlassian.net/browse/GEM5-908\n\nChange-Id: I856524b0afd30842194190f5bd69e7e6ded906b0\nSigned-off-by: Tiago Mück \u003ctiago.muck@arm.com\u003e\nReviewed-on: https://gem5-review.googlesource.com/c/public/gem5/+/42563\nReviewed-by: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nMaintainer: Jason Lowe-Power \u003cpower.jg@gmail.com\u003e\nTested-by: kokoro \u003cnoreply+kokoro@google.com\u003e\n",
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